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pluto_hdl_adi
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e95f1b282e
pluto_hdl_adi
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projects
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daq1
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AndreiGrozav
03e744f0f1
daq1_zed: Lower the adc and daq clock to 450MHz
...
The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
2017-10-04 13:01:14 +01:00
..
common
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
cpld
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
zc706
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
zed
daq1_zed: Lower the adc and daq clock to 450MHz
2017-10-04 13:01:14 +01:00
Makefile
hdlmake.pl updates
2017-07-31 09:02:12 -04:00