119 lines
3.9 KiB
Verilog
119 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_pps_receiver (
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input clk,
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input rst,
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input gps_pps,
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input up_clk,
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input up_rstn,
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output reg [31:0] up_pps_rcounter,
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input up_irq_mask,
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output reg up_irq);
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// *************************************************************************
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// 1PPS reception and reporting counter implementation
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// Note: this module should run on the core clock
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// *************************************************************************
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reg [ 2:0] gps_pps_m = 3'b0;
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reg [ 2:0] up_pps_m = 3'b0;
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reg pps_toggle = 1'b0;
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reg [31:0] free_rcounter = 32'b0;
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reg [31:0] pps_rcounter = 32'b0;
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wire pps_posedge_s;
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wire up_pps_posedge_s;
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// gps_pps is asynchronous from the clk
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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gps_pps_m <= 3'b0;
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end else begin
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gps_pps_m <= {gps_pps_m[1:0], gps_pps};
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end
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end
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assign pps_posedge_s = ~gps_pps_m[2] & gps_pps_m[1];
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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free_rcounter <= 32'b0;
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pps_rcounter <= 32'b0;
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end else if (pps_posedge_s == 1'b1) begin
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free_rcounter <= 32'b0;
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pps_rcounter <= free_rcounter;
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end else begin
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free_rcounter <= free_rcounter + 32'b1;
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end
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end
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// up_tdd_pps_rcounter CDC
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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pps_toggle <= 1'b0;
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end else if (pps_posedge_s == 1'b1) begin
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pps_toggle <= ~pps_toggle;
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end
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end
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_pps_m <= 3'b0;
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up_pps_rcounter <= 1'b0;
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end else begin
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up_pps_m <= {up_pps_m[1:0], pps_toggle};
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if ((up_pps_m[2] ^ up_pps_m[1]) == 1'b1) begin
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up_pps_rcounter <= pps_rcounter;
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end
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end
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end
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assign up_pps_posedge_s = ~up_pps_m[2] & up_pps_m[1];
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// IRQ generation
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_irq <= 1'b0;
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end else begin
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up_irq <= up_pps_posedge_s & ~up_irq_mask;
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end
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end
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endmodule
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