251 lines
9.0 KiB
Tcl
251 lines
9.0 KiB
Tcl
###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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#
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# Parameter description:
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_S : Number of samples per frame
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#
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
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# JESD204B interface configurations
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set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
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set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
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set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
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set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
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set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
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set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
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set MAX_TX_NUM_OF_LANES 4
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set MAX_RX_NUM_OF_LANES 4
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# dac peripherals
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ad_ip_instance axi_adxcvr axi_ad9144_xcvr [list \
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NUM_OF_LANES $TX_NUM_OF_LANES \
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QPLL_ENABLE 1 \
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TX_OR_RX_N 1 \
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]
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adi_axi_jesd204_tx_create axi_ad9144_jesd $TX_NUM_OF_LANES
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adi_tpl_jesd204_tx_create axi_ad9144_tpl $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH \
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ad_ip_instance util_upack2 axi_ad9144_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac axi_ad9144_dma [list \
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DMA_TYPE_SRC 0 \
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DMA_TYPE_DEST 1 \
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ID 1 \
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AXI_SLICE_SRC 0 \
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AXI_SLICE_DEST 0 \
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DMA_LENGTH_WIDTH 24 \
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DMA_2D_TRANSFER 0 \
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CYCLIC 0 \
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DMA_DATA_WIDTH_SRC 128 \
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DMA_DATA_WIDTH_DEST $dac_data_width \
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]
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ad_data_offload_create axi_ad9144_offload \
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1 \
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$dac_offload_type \
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$dac_offload_size \
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$dac_data_width \
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$dac_data_width \
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$plddr_offload_axi_data_width
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# synchronization interface
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ad_connect axi_ad9144_offload/init_req axi_ad9144_dma/m_axis_xfer_req
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ad_connect axi_ad9144_offload/sync_ext GND
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_ad9680_xcvr [list \
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NUM_OF_LANES $RX_NUM_OF_LANES \
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QPLL_ENABLE 0 \
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TX_OR_RX_N 0 \
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]
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adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
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adi_tpl_jesd204_rx_create axi_ad9680_tpl $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_parameter axi_ad9680_tpl/adc_tpl_core CONFIG.CONVERTER_RESOLUTION 14
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ad_ip_parameter axi_ad9680_tpl/adc_tpl_core CONFIG.TWOS_COMPLEMENT 0
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ad_ip_instance util_cpack2 axi_ad9680_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac axi_ad9680_dma [list \
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DMA_TYPE_SRC 1 \
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DMA_TYPE_DEST 0 \
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ID 0 \
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AXI_SLICE_SRC 0 \
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AXI_SLICE_DEST 0 \
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SYNC_TRANSFER_START 0 \
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DMA_LENGTH_WIDTH 24 \
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DMA_2D_TRANSFER 0 \
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CYCLIC 0 \
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DMA_DATA_WIDTH_SRC $adc_data_width \
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DMA_DATA_WIDTH_DEST 64 \
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]
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ad_data_offload_create axi_ad9680_offload \
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0 \
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$adc_offload_type \
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$adc_offload_size \
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$adc_data_width \
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$adc_data_width \
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$plddr_offload_axi_data_width
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# synchronization interface
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ad_connect axi_ad9680_offload/init_req axi_ad9680_dma/s_axis_xfer_req
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ad_connect axi_ad9680_offload/sync_ext GND
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# shared transceiver core
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ad_ip_instance util_adxcvr util_daq2_xcvr [list \
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RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \
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TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES \
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QPLL_REFCLK_DIV 1 \
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QPLL_FBDIV_RATIO 1 \
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QPLL_FBDIV 0x30 \
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RX_OUT_DIV 1 \
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TX_OUT_DIV 1 \
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RX_DFE_LPM_CFG 0x0104 \
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RX_CDR_CFG 0x0B000023FF10400020 \
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]
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ad_connect $sys_cpu_resetn util_daq2_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_daq2_xcvr/up_clk
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# reference clocks & resets
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create_bd_port -dir I tx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_0
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ad_xcvrpll tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
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# connections (dac)
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ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1} {} {} $MAX_TX_NUM_OF_LANES
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ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_tpl/link_clk
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ad_connect axi_ad9144_jesd/tx_data axi_ad9144_tpl/link
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ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/clk
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ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_upack/reset
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ad_connect axi_ad9144_tpl/dac_dunf axi_ad9144_upack/fifo_rd_underflow
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ad_connect axi_ad9144_tpl/dac_valid_0 axi_ad9144_upack/fifo_rd_en
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect axi_ad9144_tpl/dac_enable_$i axi_ad9144_upack/enable_$i
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ad_connect axi_ad9144_tpl/dac_data_$i axi_ad9144_upack/fifo_rd_data_$i
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}
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ad_connect $sys_cpu_clk axi_ad9144_offload/s_axi_aclk
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ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_offload/m_axis_aclk
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ad_connect $sys_cpu_clk axi_ad9144_offload/s_axis_aclk
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ad_connect $sys_cpu_clk axi_ad9144_dma/m_axis_aclk
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ad_connect $sys_cpu_resetn axi_ad9144_offload/s_axi_aresetn
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ad_connect axi_ad9144_jesd_rstgen/peripheral_aresetn axi_ad9144_offload/m_axis_aresetn
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ad_connect $sys_cpu_resetn axi_ad9144_offload/s_axis_aresetn
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ad_connect $sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
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ad_connect axi_ad9144_upack/s_axis axi_ad9144_offload/m_axis
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ad_connect axi_ad9144_offload/s_axis axi_ad9144_dma/m_axis
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# connections (adc)
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ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd {} {} {} $MAX_RX_NUM_OF_LANES
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ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_tpl/link_clk
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ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_tpl/link_sof
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ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl/link_data
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ad_connect axi_ad9680_jesd/rx_data_tvalid axi_ad9680_tpl/link_valid
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ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
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ad_connect axi_ad9680_tpl/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect axi_ad9680_tpl/adc_enable_$i axi_ad9680_cpack/enable_$i
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ad_connect axi_ad9680_tpl/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
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}
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ad_connect axi_ad9680_tpl/adc_dovf axi_ad9680_cpack/fifo_wr_overflow
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ad_connect $sys_cpu_clk axi_ad9680_offload/s_axi_aclk
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ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_offload/s_axis_aclk
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ad_connect $sys_cpu_clk axi_ad9680_offload/m_axis_aclk
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ad_connect $sys_cpu_clk axi_ad9680_dma/s_axis_aclk
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ad_connect $sys_cpu_resetn axi_ad9680_offload/s_axi_aresetn
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ad_connect axi_ad9680_jesd_rstgen/peripheral_aresetn axi_ad9680_offload/s_axis_aresetn
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ad_connect $sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
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ad_connect $sys_cpu_resetn axi_ad9680_offload/m_axis_aresetn
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ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_offload/i_data_offload/s_axis_valid
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ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_offload/i_data_offload/s_axis_data
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ad_connect axi_ad9680_offload/m_axis axi_ad9680_dma/s_axis
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
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ad_cpu_interconnect 0x44A04000 axi_ad9144_tpl
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ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
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ad_cpu_interconnect 0x7c440000 axi_ad9144_offload
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ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl
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ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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ad_cpu_interconnect 0x7c460000 axi_ad9680_offload
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9680_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9144_dma/m_src_axi
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ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9680_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-10 mb-15 axi_ad9144_jesd/irq
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ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
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