89 lines
2.8 KiB
Verilog
89 lines
2.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module m2k_spi (
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// 4-wire
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input ad9963_csn,
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input adf4360_cs,
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input spi_clk,
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input spi_mosi,
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output spi_miso,
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// 3-wire
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inout spi_sdio
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);
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// check on rising edge and change on falling edge
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always @(posedge spi_clk or posedge ad9963_csn) begin
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if (ad9963_csn == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= spi_count + 1'b1;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk or posedge ad9963_csn) begin
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if (ad9963_csn == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if ((spi_count == 6'd16) && (ad9963_csn == 1'b0)) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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// io buffers
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assign spi_miso = spi_sdio;
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assign spi_sdio = (spi_enable == 1'b1) ? 1'bz : spi_mosi;
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endmodule
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