292 lines
8.5 KiB
Verilog
292 lines
8.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9434 (
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// physical interface
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adc_clk_in_p,
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adc_clk_in_n,
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adc_data_in_p,
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adc_data_in_n,
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adc_or_in_p,
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adc_or_in_n,
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// delay interface
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delay_clk,
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// dma interface
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adc_clk,
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adc_enable,
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adc_valid,
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adc_data,
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adc_dovf,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rready);
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// parameters
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localparam SERIES7 = 0;
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localparam SERIES6 = 1;
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parameter PCORE_ID = 0;
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parameter PCORE_DEVTYPE = SERIES7;
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parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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// physical interface
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input adc_clk_in_p;
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input adc_clk_in_n;
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input [11:0] adc_data_in_p;
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input [11:0] adc_data_in_n;
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input adc_or_in_p;
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input adc_or_in_n;
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// delay interface
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input delay_clk;
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// dma interface
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output adc_clk;
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output adc_valid;
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output adc_enable;
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output [63:0] adc_data;
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input adc_dovf;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire mmcm_rst;
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wire up_clk;
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wire adc_clk;
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wire drp_clk;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s;
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wire up_wack_s;
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wire up_rack_s;
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wire [ 1:0] up_status_pn_err_s;
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wire [ 1:0] up_status_pn_oos_s;
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wire [ 1:0] up_status_or_s;
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wire adc_status_s;
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wire delay_rst_s;
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wire delay_sel_s;
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wire delay_rwn_s;
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wire [ 7:0] delay_addr_s;
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wire [ 4:0] delay_wdata_s;
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wire [ 4:0] delay_rdata_s;
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wire delay_ack_t_s;
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wire delay_locked_s;
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wire drp_sel_s;
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wire drp_rst_s;
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wire drp_wr_s;
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wire [11:0] drp_addr_s;
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wire [15:0] drp_wdata_s;
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wire [15:0] drp_rdata_s;
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wire drp_ready_s;
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wire drp_locked_s;
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wire [47:0] adc_data_if_s;
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wire adc_or_if_s;
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// clock/reset assignments
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign drp_clk = up_clk;
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// single channel always enable
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assign adc_enable = 1'b1;
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axi_ad9434_if #(
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.PCORE_DEVTYPE(PCORE_DEVTYPE),
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.PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP))
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i_if(
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.adc_clk_in_p(adc_clk_in_p),
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.adc_clk_in_n(adc_clk_in_n),
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.adc_data_in_p(adc_data_in_p),
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.adc_data_in_n(adc_data_in_n),
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.adc_or_in_p(adc_or_in_p),
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.adc_or_in_n(adc_or_in_n),
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.adc_data(adc_data_if_s),
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.adc_or(adc_or_if_s),
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.adc_clk(adc_clk),
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.adc_rst(adc_rst),
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.adc_status(adc_status_s),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst_s),
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.delay_sel(delay_sel_s),
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.delay_rwn(delay_rwn_s),
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.delay_addr(delay_addr_s),
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.delay_wdata(delay_wdata_s),
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.delay_rdata(delay_rdata_s),
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.delay_ack_t(delay_ack_t_s),
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.delay_locked(delay_locked_s),
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.mmcm_rst(mmcm_rst),
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.drp_clk(drp_clk),
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.drp_rst(drp_rst_s),
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.drp_sel(drp_sel_s),
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.drp_wr(drp_wr_s),
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.drp_addr(drp_addr_s),
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.drp_wdata(drp_wdata_s),
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.drp_rdata(drp_rdata_s),
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.drp_ready(drp_ready_s),
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.drp_locked(drp_locked_s));
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// common processor control
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axi_ad9434_core #(.PCORE_ID(PCORE_ID))
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i_core (
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.adc_clk(adc_clk),
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.adc_data(adc_data_if_s),
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.adc_or(adc_or_if_s),
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.mmcm_rst (mmcm_rst),
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.adc_rst (adc_rst),
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.adc_status (adc_status_s),
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.dma_dvalid (adc_valid),
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.dma_data (adc_data),
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.dma_dovf (adc_dovf),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst_s),
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.delay_sel (delay_sel_s),
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.delay_rwn (delay_rwn_s),
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.delay_addr (delay_addr_s),
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.delay_wdata (delay_wdata_s),
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.delay_rdata (delay_rdata_s),
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.delay_ack_t (delay_ack_t_s),
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.delay_locked (delay_locked_s),
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.drp_clk (drp_clk),
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.drp_rst (drp_rst_s),
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.drp_sel (drp_sel_s),
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.drp_wr (drp_wr_s),
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.drp_addr (drp_addr_s),
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.drp_wdata (drp_wdata_s),
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.drp_rdata (drp_rdata_s),
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.drp_ready (drp_ready_s),
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.drp_locked (drp_locked_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata_s),
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.up_wack (up_wack_s),
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.up_raddr (up_raddr_s),
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.up_rreq (up_rreq_s),
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.up_rack (up_rack_s));
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endmodule
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