Adrian Costina a0d27a117c usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints		2014-10-22 13:20:44 +03:00
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system_bd.tcl	usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.	2014-09-16 15:56:19 -04:00
system_constr.xdc	usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints	2014-10-22 13:20:44 +03:00
system_project.tcl	usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.	2014-09-16 15:56:19 -04:00
system_top.v	usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization	2014-09-23 22:44:33 -04:00