Istvan Csomortani f9c4283f45 stratix10soc: Initial commit of base design ... Note: Currently we have a engineering sample version 2 board.		2020-09-09 14:15:37 +03:00
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adi_board.tcl	adi_board: fixed ddr memory mapping for microblaze projects	2020-01-13 12:25:23 +02:00
adi_env.tcl	scripts/adi_env.tcl: print in logs system variables are used	2020-05-20 19:07:23 +03:00
adi_intel_msg.tcl	scripts/intel: Add message severity definition file	2020-08-25 14:46:52 +03:00
adi_make.tcl	Add adi make(build) scripts	2018-12-11 14:02:11 +02:00
adi_make_boot_bin.tcl	Add adi make(build) scripts	2018-12-11 14:02:11 +02:00
adi_project_intel.tcl	stratix10soc: Initial commit of base design	2020-09-09 14:15:37 +03:00
adi_project_xilinx.tcl	adi_project_xilinx.tcl: discover all timing failures	2020-05-26 14:47:38 +03:00
adi_tquest.tcl	adi_tquest: Improve the timing report generation	2018-08-08 15:09:19 +03:00
adi_xilinx_msg.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
project-intel.mk	scripts/project-intel: Update CLEAN target	2020-08-11 10:14:18 +03:00
project-toplevel.mk	Add quiet mode to the Makefile system	2018-04-11 15:09:54 +03:00
project-xilinx.mk	projects/scripts/*xilinx*: Generate report utilization extra files	2019-10-18 13:42:34 +03:00