181 lines
7.4 KiB
Tcl
181 lines
7.4 KiB
Tcl
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# dac interface
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create_bd_port -dir I dac_clk_in_p
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create_bd_port -dir I dac_clk_in_n
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create_bd_port -dir O dac_clk_out_p
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create_bd_port -dir O dac_clk_out_n
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create_bd_port -dir O dac_frame_out_p
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create_bd_port -dir O dac_frame_out_n
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create_bd_port -dir O -from 15 -to 0 dac_data_out_p
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create_bd_port -dir O -from 15 -to 0 dac_data_out_n
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# adc interface
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create_bd_port -dir I adc_clk_in_p
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create_bd_port -dir I adc_clk_in_n
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create_bd_port -dir I adc_or_in_p
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create_bd_port -dir I adc_or_in_n
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create_bd_port -dir I -from 13 -to 0 adc_data_in_p
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create_bd_port -dir I -from 13 -to 0 adc_data_in_n
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# reference clock
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create_bd_port -dir O ref_clk
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# dma interface
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create_bd_port -dir O dac_clk
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create_bd_port -dir O dac_valid_0
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create_bd_port -dir O dac_enable_0
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create_bd_port -dir I -from 63 -to 0 dac_ddata_0
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create_bd_port -dir O dac_valid_1
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create_bd_port -dir O dac_enable_1
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create_bd_port -dir I -from 63 -to 0 dac_ddata_1
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create_bd_port -dir I dac_dma_rd
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create_bd_port -dir O -from 63 -to 0 dac_dma_rdata
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_valid_0
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create_bd_port -dir O adc_enable_0
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create_bd_port -dir O -from 15 -to 0 adc_data_0
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create_bd_port -dir O adc_valid_1
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create_bd_port -dir O adc_enable_1
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create_bd_port -dir O -from 15 -to 0 adc_data_1
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create_bd_port -dir I adc_dma_wr
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create_bd_port -dir I -from 31 -to 0 adc_dma_wdata
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# dac peripherals
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set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122]
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set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_FIFO_SIZE {16}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma
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# adc peripherals
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set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643]
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set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_FIFO_SIZE {16}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
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# reference clock
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set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 refclk_clkgen]
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen
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set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen
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set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen
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set_property -dict [list CONFIG.USE_LOCKED {false} ] $refclk_clkgen
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set_property -dict [list CONFIG.USE_RESET {false} ] $refclk_clkgen
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# reference clock connections
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ad_connect sys_200m_clk refclk_clkgen/clk_in1
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ad_connect ref_clk refclk_clkgen/clk_out1
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# connections (dac)
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ad_connect dac_clk axi_ad9122/dac_div_clk
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ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk
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ad_connect dac_clk_in_p axi_ad9122/dac_clk_in_p
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ad_connect dac_clk_in_n axi_ad9122/dac_clk_in_n
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ad_connect dac_clk_out_p axi_ad9122/dac_clk_out_p
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ad_connect dac_clk_out_n axi_ad9122/dac_clk_out_n
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ad_connect dac_frame_out_p axi_ad9122/dac_frame_out_p
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ad_connect dac_frame_out_n axi_ad9122/dac_frame_out_n
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ad_connect dac_data_out_p axi_ad9122/dac_data_out_p
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ad_connect dac_data_out_n axi_ad9122/dac_data_out_n
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ad_connect axi_ad9122/dac_valid_0 dac_valid_0
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ad_connect axi_ad9122/dac_enable_0 dac_enable_0
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ad_connect axi_ad9122/dac_ddata_0 dac_ddata_0
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ad_connect axi_ad9122/dac_valid_1 dac_valid_1
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ad_connect axi_ad9122/dac_enable_1 dac_enable_1
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ad_connect axi_ad9122/dac_ddata_1 dac_ddata_1
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ad_connect axi_ad9122/dac_dunf axi_ad9122_dma/fifo_rd_underflow
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ad_connect dac_dma_rd axi_ad9122_dma/fifo_rd_en
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ad_connect dac_dma_rdata axi_ad9122_dma/fifo_rd_dout
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# connections (adc)
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p_sys_wfifo [current_bd_instance .] sys_wfifo 32 64
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ad_connect adc_clk axi_ad9643/adc_clk
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ad_connect adc_clk sys_wfifo/adc_clk
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ad_connect sys_200m_clk axi_ad9643/delay_clk
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ad_connect sys_200m_clk axi_ad9643_dma/fifo_wr_clk
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ad_connect sys_200m_clk sys_wfifo/dma_clk
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ad_connect axi_ad9643/adc_rst sys_wfifo/adc_rst
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ad_connect adc_clk_in_p axi_ad9643/adc_clk_in_p
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ad_connect adc_clk_in_n axi_ad9643/adc_clk_in_n
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ad_connect adc_or_in_p axi_ad9643/adc_or_in_p
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ad_connect adc_or_in_n axi_ad9643/adc_or_in_n
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ad_connect adc_data_in_p axi_ad9643/adc_data_in_p
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ad_connect adc_data_in_n axi_ad9643/adc_data_in_n
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ad_connect adc_valid_0 axi_ad9643/adc_valid_0
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ad_connect adc_enable_0 axi_ad9643/adc_enable_0
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ad_connect adc_data_0 axi_ad9643/adc_data_0
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ad_connect adc_valid_1 axi_ad9643/adc_valid_1
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ad_connect adc_enable_1 axi_ad9643/adc_enable_1
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ad_connect adc_data_1 axi_ad9643/adc_data_1
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ad_connect axi_ad9643/adc_dovf sys_wfifo/adc_wovf
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ad_connect adc_dma_wr sys_wfifo/adc_wr
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ad_connect adc_dma_wdata sys_wfifo/adc_wdata
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ad_connect sys_wfifo/dma_wr axi_ad9643_dma/fifo_wr_en
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ad_connect sys_wfifo/dma_wdata axi_ad9643_dma/fifo_wr_din
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ad_connect sys_wfifo/dma_wovf axi_ad9643_dma/fifo_wr_overflow
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ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
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ad_connect sys_cpu_resetn axi_ad9643_dma/m_dest_axi_aresetn
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# address map
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ad_cpu_interconnect 0x74200000 axi_ad9122
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ad_cpu_interconnect 0x79020000 axi_ad9643
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ad_cpu_interconnect 0x7c400000 axi_ad9643_dma
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ad_cpu_interconnect 0x7c420000 axi_ad9122_dma
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ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_200m_clk axi_ad9643_dma/m_dest_axi
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ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
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# interrupts
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ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq
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ad_cpu_interrupt ps-13 mb-13 axi_ad9643_dma/irq
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# ila (adc)
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
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set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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ad_connect sys_200m_clk ila_adc/clk
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ad_connect sys_wfifo/dma_wr ila_adc/PROBE0
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ad_connect sys_wfifo/dma_wdata ila_adc/PROBE1
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