Istvan Csomortani 31a5c674f2 fmcomms2: Update constraints file paths		2017-03-30 16:16:02 +03:00
..
altera	altera- cmos cores	2016-10-31 13:13:48 -04:00
xilinx	xilinx/axi_ad9361_lvds_if: Remove ila	2016-10-11 18:13:45 +03:00
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
axi_ad9361.v	axi_ad9361- add receive init delay	2017-03-13 16:28:38 -04:00
axi_ad9361_constr.sdc	library/axi_ad9361: tdd false paths	2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc	axi_ad9361: Define CDC constraint for tdd_sync	2017-02-24 11:24:07 +02:00
axi_ad9361_delay.tcl	move/rename - delay script belongs to ad9361	2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl	alt_serdes- a10 ddio fixes	2016-11-01 12:41:25 -04:00
axi_ad9361_ip.tcl	fmcomms2: Update constraints file paths	2017-03-30 16:16:02 +03:00
axi_ad9361_rx.v	axi_ad9361- add receive init delay	2017-03-13 16:28:38 -04:00
axi_ad9361_rx_channel.v	ad9361- adc data path split	2016-09-23 13:42:14 -04:00
axi_ad9361_rx_pnmon.v	hdl/library: Update the IP parameters	2015-08-19 14:11:47 +03:00
axi_ad9361_tdd.v	axi_ad9361_tdd: Register the tdd_sync_cntr output	2017-02-23 11:31:23 +02:00
axi_ad9361_tdd_if.v	hdl/library: Update the IP parameters	2015-08-19 14:11:47 +03:00
axi_ad9361_tx.v	axi_ad9361- add receive init delay	2017-03-13 16:28:38 -04:00
axi_ad9361_tx_channel.v	ad9361- dac data path split	2016-09-23 16:13:46 -04:00