Istvan Csomortani ac2e5a9dac constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.		2017-02-24 13:43:32 +02:00
..
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
axi_gpreg.v	library axi-slave missing protection signal added	2016-07-22 12:54:27 -04:00
axi_gpreg_clock_mon.v	axi_gpreg: add buffer enable	2015-11-05 11:28:35 -05:00
axi_gpreg_constr.xdc	constraints: Update constraints	2017-02-24 13:43:32 +02:00
axi_gpreg_io.v	axi_gpreg- added	2015-11-03 14:28:59 -05:00
axi_gpreg_ip.tcl	axi_gpreg: compile fixes	2015-11-03 14:29:00 -05:00