Istvan Csomortani ac2e5a9dac constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.		2017-02-24 13:43:32 +02:00
..
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
util_rfifo.v	rfifo- buffer 1 seg before read	2016-07-12 10:24:22 -04:00
util_rfifo_constr.sdc	rfifo- buffer 1 seg before read	2016-07-12 10:24:22 -04:00
util_rfifo_constr.xdc	constraints: Update constraints	2017-02-24 13:43:32 +02:00
util_rfifo_hw.tcl	util_rfifo: Patch up the description of Altera IP	2016-08-08 16:39:25 +03:00
util_rfifo_ip.tcl	util_rfifo: updates	2016-05-16 12:19:38 -04:00