Istvan Csomortani 79b6ba29ce all: Rename altera to intel		2019-06-29 06:53:51 +03:00
..
adi_jesd204_glue.v	library: Add `timescale to modules that are missing it	2019-05-15 15:37:44 +03:00
adi_jesd204_glue_hw.tcl	altera: adi_jesd204: Add support for more than 6 transmit lanes	2018-11-28 11:33:37 +02:00