Go to file

Lars-Peter Clausen ecc498313c fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects We have enough bridge interconnect to give each DMA its own, so use them. This makes sure that they do not interfere with each others transfers to much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a much faster frequency then what we are able to use in the fabric. So its better to do the arbitration on that side of the bus to make sure that we can utilize the buses in the FPGA fabric to the maximum for each DMA core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2014-09-12 16:14:07 +02:00
library	util_dac_unpack: Make number of channels and channel width configurable	2014-09-12 16:14:04 +02:00
projects	fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects	2014-09-12 16:14:07 +02:00
.gitignore	a5soc: increase pipeline for qsys	2014-05-04 10:38:53 -04:00
LICENSE	Update LICENSE	2014-03-11 15:06:52 -04:00
README.md	Add a link to EngineerZone	2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga