ecc498313c
We have enough bridge interconnect to give each DMA its own, so use them. This makes sure that they do not interfere with each others transfers to much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a much faster frequency then what we are able to use in the fabric. So its better to do the arbitration on that side of the bus to make sure that we can utilize the buses in the FPGA fabric to the maximum for each DMA core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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ac701 | ||
c5soc | ||
common | ||
kc705 | ||
mitx045 | ||
ml605 | ||
vc707 | ||
zc702 | ||
zc706 | ||
zed |