187 lines
5.6 KiB
Verilog
187 lines
5.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
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`timescale 1ps/1ps
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module DSP48E1 (
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ACOUT,
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BCOUT,
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CARRYCASCOUT,
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CARRYOUT,
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MULTSIGNOUT,
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OVERFLOW,
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P,
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PATTERNBDETECT,
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PATTERNDETECT,
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PCOUT,
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UNDERFLOW,
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A,
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ACIN,
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ALUMODE,
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B,
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BCIN,
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C,
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CARRYCASCIN,
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CARRYIN,
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CARRYINSEL,
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CEA1,
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CEA2,
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CEAD,
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CEALUMODE,
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CEB1,
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CEB2,
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CEC,
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CECARRYIN,
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CECTRL,
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CED,
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CEINMODE,
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CEM,
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CEP,
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CLK,
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D,
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INMODE,
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MULTSIGNIN,
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OPMODE,
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PCIN,
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RSTA,
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RSTALLCARRYIN,
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RSTALUMODE,
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RSTB,
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RSTC,
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RSTCTRL,
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RSTD,
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RSTINMODE,
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RSTM,
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RSTP);
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parameter ACASCREG = 1;
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parameter ADREG = 1;
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parameter ALUMODEREG = 1;
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parameter AREG = 1;
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parameter AUTORESET_PATDET = "NO_RESET";
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parameter A_INPUT = "DIRECT";
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parameter BCASCREG = 1;
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parameter BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter CARRYINREG = 1;
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parameter CARRYINSELREG = 1;
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parameter CREG = 1;
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parameter DREG = 1;
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parameter INMODEREG = 1;
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parameter MASK = 'h3fffffffffff;
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parameter MREG = 1;
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parameter OPMODEREG = 1;
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parameter PATTERN = 0;
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parameter PREG = 1;
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parameter SEL_MASK = "MASK";
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parameter SEL_PATTERN = "PATTERN";
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parameter USE_DPORT = 0;
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parameter USE_MULT = "MULTIPLY";
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parameter USE_PATTERN_DETECT = "NO_PATDET";
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parameter USE_SIMD = "ONE48";
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output [29:0] ACOUT;
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output [17:0] BCOUT;
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output CARRYCASCOUT;
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output [ 3:0] CARRYOUT;
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output MULTSIGNOUT;
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output OVERFLOW;
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output [47:0] P;
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output PATTERNBDETECT;
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output PATTERNDETECT;
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output [47:0] PCOUT;
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output UNDERFLOW;
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input [29:0] A;
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input [29:0] ACIN;
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input [ 3:0] ALUMODE;
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input [17:0] B;
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input [17:0] BCIN;
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input [47:0] C;
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input CARRYCASCIN;
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input CARRYIN;
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input [ 2:0] CARRYINSEL;
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input CEA1;
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input CEA2;
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input CEAD;
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input CEALUMODE;
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input CEB1;
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input CEB2;
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input CEC;
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input CECARRYIN;
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input CECTRL;
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input CED;
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input CEINMODE;
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input CEM;
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input CEP;
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input CLK;
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input [24:0] D;
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input [ 4:0] INMODE;
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input MULTSIGNIN;
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input [ 6:0] OPMODE;
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input [47:0] PCIN;
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input RSTA;
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input RSTALLCARRYIN;
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input RSTALUMODE;
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input RSTB;
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input RSTC;
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input RSTCTRL;
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input RSTD;
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input RSTINMODE;
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input RSTM;
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input RSTP;
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assign ACOUT = 30'd0;
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assign BCOUT = 18'd0;
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assign CARRYCASCOUT = 1'd0;
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assign CARRYOUT = 4'd0;
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assign MULTSIGNOUT = 1'd0;
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assign OVERFLOW = 1'd0;
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assign P = 48'd0;
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assign PATTERNBDETECT = 1'd0;
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assign PATTERNDETECT = 1'd0;
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assign PCOUT = 48'd0;
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assign UNDERFLOW = 1'd0;
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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