113 lines
4.1 KiB
Verilog
113 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// both inputs are considered unsigned 16 bits-
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// ddata is delay matched generic data
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`timescale 1ps/1ps
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module ad_mul_u16 (
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// data_p = data_a * data_b;
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clk,
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data_a,
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data_b,
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data_p,
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// delay interface
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ddata_in,
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ddata_out);
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// delayed data bus width
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parameter DELAY_DATA_WIDTH = 16;
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localparam DW = DELAY_DATA_WIDTH - 1;
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// data_p = data_a * data_b;
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input clk;
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input [15:0] data_a;
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input [15:0] data_b;
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output [31:0] data_p;
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// delay interface
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input [DW:0] ddata_in;
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output [DW:0] ddata_out;
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// internal registers
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reg [DW:0] p1_ddata = 'd0;
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reg [DW:0] p2_ddata = 'd0;
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reg [DW:0] ddata_out = 'd0;
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// internal signals
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// a/b reg, m-reg, p-reg delay match
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always @(posedge clk) begin
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p1_ddata <= ddata_in;
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p2_ddata <= p1_ddata;
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ddata_out <= p2_ddata;
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end
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lpm_mult i_mult_macro (
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.clock (clk),
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.dataa (data_a),
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.datab (data_b),
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.result (data_p),
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.aclr (1'b0),
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.clken (1'b1),
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.sum (1'b0));
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defparam
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lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
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lpm_mult_component.lpm_pipeline = 3,
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lpm_mult_component.lpm_representation = "UNSIGNED",
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lpm_mult_component.lpm_type = "LPM_MULT",
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lpm_mult_component.lpm_widtha = 16,
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lpm_mult_component.lpm_widthb = 16,
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lpm_mult_component.lpm_widthp = 32;
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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