147 lines
5.2 KiB
Verilog
147 lines
5.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_xfer_status (
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// up interface
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up_rstn,
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up_clk,
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up_data_status,
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// device interface
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d_rst,
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d_clk,
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d_data_status);
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// parameters
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parameter DATA_WIDTH = 8;
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localparam DW = DATA_WIDTH - 1;
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// up interface
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input up_rstn;
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input up_clk;
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output [DW:0] up_data_status;
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// device interface
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input d_rst;
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input d_clk;
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input [DW:0] d_data_status;
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// internal registers
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reg d_xfer_state_m1 = 'd0;
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reg d_xfer_state_m2 = 'd0;
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reg d_xfer_state = 'd0;
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reg [ 5:0] d_xfer_count = 'd0;
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reg d_xfer_toggle = 'd0;
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reg [DW:0] d_xfer_data = 'd0;
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reg [DW:0] d_acc_data = 'd0;
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reg up_xfer_toggle_m1 = 'd0;
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reg up_xfer_toggle_m2 = 'd0;
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reg up_xfer_toggle_m3 = 'd0;
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reg up_xfer_toggle = 'd0;
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reg [DW:0] up_data_status = 'd0;
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// internal signals
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wire d_xfer_enable_s;
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wire up_xfer_toggle_s;
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// device status transfer
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assign d_xfer_enable_s = d_xfer_state ^ d_xfer_toggle;
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always @(posedge d_clk) begin
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if (d_rst == 1'b1) begin
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d_xfer_state_m1 <= 'd0;
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d_xfer_state_m2 <= 'd0;
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d_xfer_state <= 'd0;
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d_xfer_count <= 'd0;
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d_xfer_toggle <= 'd0;
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d_xfer_data <= 'd0;
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d_acc_data <= 'd0;
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end else begin
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d_xfer_state_m1 <= up_xfer_toggle;
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d_xfer_state_m2 <= d_xfer_state_m1;
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d_xfer_state <= d_xfer_state_m2;
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d_xfer_count <= d_xfer_count + 1'd1;
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if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin
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d_xfer_toggle <= ~d_xfer_toggle;
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d_xfer_data <= d_acc_data;
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end
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if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin
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d_acc_data <= d_data_status;
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end else begin
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d_acc_data <= d_acc_data | d_data_status;
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end
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end
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end
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assign up_xfer_toggle_s = up_xfer_toggle_m3 ^ up_xfer_toggle_m2;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_xfer_toggle_m1 <= 'd0;
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up_xfer_toggle_m2 <= 'd0;
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up_xfer_toggle_m3 <= 'd0;
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up_xfer_toggle <= 'd0;
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up_data_status <= 'd0;
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end else begin
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up_xfer_toggle_m1 <= d_xfer_toggle;
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up_xfer_toggle_m2 <= up_xfer_toggle_m1;
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up_xfer_toggle_m3 <= up_xfer_toggle_m2;
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up_xfer_toggle <= up_xfer_toggle_m3;
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if (up_xfer_toggle_s == 1'b1) begin
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up_data_status <= d_xfer_data;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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