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ATofan ee56db8d50 FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file 
tcl: FCLK2 was modified from 100 MHz to 125 MHz.

xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz)
 		2014-03-14 16:27:56 +02:00
library axi_dmac: Add support for DMA bus widths other than 64 bit 2014-03-13 13:20:10 +01:00
projects FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file 2014-03-14 16:27:56 +02:00
.gitignore added gitignore 2014-03-05 10:47:16 -05:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Update README.md 2014-03-13 14:03:15 -04:00

README.md

hdl

Analog Devices HDL libraries and projects

http://wiki.analog.com/resources/fpga/docs/hdl/github

http://wiki.analog.com/resources/fpga/docs/hdl/regmap