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When the source and destination bus widths don't match a resize block is inserted on the side of the narrower bus. This resize block can contain partial data. To ensure that there is no residual partial data is left in the resize block after a transfer shutdown the resize block is reset when the DMA is disabled. Currently this is implemented by tying the reset signal of the resize block to the enable signal of the DMA. This enable signal is only a indicator though that the DMA should shutdown. For a proper shutdown outstanding transactions still need to be completed. The data that is in the resize block might be required to complete those transactions. So performing the reset when the enable signal goes low can lead to a situation where the DMA tries to complete a transaction but can't do it because the data required to do so has been erased by resetting the resize block. This leads to a dead lock and the system has to be rebooted to recover from it. To solve this use the sync_id signal to reset the resize block. The sync_id signal will only be asserted when both the destination and source side module have indicated that they are ready to be reset and there are no more pending transactions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects.
Getting started
This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.
Prerequisites
or
Please make sure that you have the required tool version.
How to build a project
For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.
To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:
[~]cd projects/fmcomms2/zc706
[~]make
A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build
Software
In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.
Which branch should I use?
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If you want to use the most stable code base, always use the latest release branch.
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If you want to use the greatest and latest, check out the master branch.
License
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
See LICENSE for more details. The separate license files cab be found here:
Comprehensive user guide
See HDL User Guide for a more detailed guide.
Support
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