Laszlo Nagy eedb2ce0f4 avl_dacfifo: bundle AXIS signals into bus		2019-05-16 13:27:19 +03:00
..
adi_jesd204	library: Add `timescale to modules that are missing it	2019-05-15 15:37:44 +03:00
avl_adxcfg	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
avl_adxcvr	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
avl_adxcvr_octet_swap	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
avl_adxphy	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
avl_dacfifo	avl_dacfifo: bundle AXIS signals into bus	2019-05-16 13:27:19 +03:00
axi_adxcvr	dev info parameter update: Increase pcore version	2019-03-30 11:26:11 +02:00
common	ad_rst: Fix constraints for Intel designs	2018-08-09 10:26:18 +03:00
jesd204_phy	altera: adi_jesd204: Add support for more than 6 transmit lanes	2018-11-28 11:33:37 +02:00