6.9 KiB
6.9 KiB
| 1 | Address | ||||||
|---|---|---|---|---|---|---|---|
| 2 | DWORD | BYTE | Bits | Name | Type | Default | Description |
| 3 | 0x0100 | 0x0400 | REG_CHAN_CNTRL | ADC Interface Control & Status | |||
| 4 | [11] | ADC_LB_OWR | RW | 0x0 | If set, forces ADC_DATA_SEL to 1, enabling data loopback | ||
| 5 | [10] | ADC_PN_SEL_OWR | RW | 0x0 | If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored | ||
| 6 | [9] | IQCOR_ENB | RW | 0x0 | if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | ||
| 7 | [8] | DCFILT_ENB | RW | 0x0 | if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). | ||
| 8 | [6] | FORMAT_SIGNEXT | RW | 0x0 | if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). | ||
| 9 | [5] | FORMAT_TYPE | RW | 0x0 | Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). | ||
| 10 | [4] | FORMAT_ENABLE | RW | 0x0 | Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). | ||
| 11 | [3] | RESERVED | RO | 0x0 | Reserved for backward compatibility. | ||
| 12 | [2] | RESERVED | RO | 0x0 | Reserved for backward compatibility. | ||
| 13 | [1] | ADC_PN_TYPE_OWR | RW | 0x0 | If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored | ||
| 14 | [0] | ENABLE | RW | 0x0 | If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. | ||
| 15 | 0x0101 | 0x0404 | REG_CHAN_STATUS | ADC Interface Control & Status | |||
| 16 | [12] | CRC_ERR | RW1C | 0x0 | CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards. | ||
| 17 | [11:4] | STATUS_HEADER | RO | 0x00 | The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x). | ||
| 18 | [2] | PN_ERR | RW1C | 0x0 | PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared. | ||
| 19 | [1] | PN_OOS | RW1C | 0x0 | PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern. | ||
| 20 | [0] | OVER_RANGE | RW1C | 0x0 | If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. | ||
| 21 | 0x0102 | 0x0408 | REG_CHAN_RAW_DATA | ADC Raw Data Reading | |||
| 22 | [31:0] | ADC_READ_DATA[31:0] | RO | 0x0000 | Raw data read from the ADC. | ||
| 23 | 0x0104 | 0x0410 | REG_CHAN_CNTRL_1 | ADC Interface Control & Status | |||
| 24 | [31:16] | DCFILT_OFFSET[15:0] | RW | 0x0000 | DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). | ||
| 25 | [15:0] | DCFILT_COEFF[15:0] | RW | 0x0000 | DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). | ||
| 26 | 0x0105 | 0x0414 | REG_CHAN_CNTRL_2 | ADC Interface Control & Status | |||
| 27 | [31:16] | IQCOR_COEFF_1[15:0] | RW | 0x0000 | IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | ||
| 28 | [15:0] | IQCOR_COEFF_2[15:0] | RW | 0x0000 | IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | ||
| 29 | 0x0106 | 0x0418 | REG_CHAN_CNTRL_3 | ADC Interface Control & Status | |||
| 30 | [19:16] | ADC_PN_SEL[3:0] | RW | 0x0 | Selects the PN monitor sequence type (available only if ADC supports it). - 0x0: pn9a (device specific, modified pn9) - 0x1: pn23a (device specific, modified pn23) - 0x4: pn7 (standard O.150) - 0x5: pn15 (standard O.150) - 0x6: pn23 (standard O.150) - 0x7: pn31 (standard O.150) - 0x9: pnX (device specific, e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) | ||
| 31 | [3:0] | ADC_DATA_SEL[3:0] | RW | 0x0 | Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC) | ||
| 32 | 0x0108 | 0x0420 | REG_CHAN_USR_CNTRL_1 | ADC Interface Control & Status | |||
| 33 | [25] | USR_DATATYPE_BE | RO | 0x0 | The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | ||
| 34 | [24] | USR_DATATYPE_SIGNED | RO | 0x0 | The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | ||
| 35 | [23:16] | USR_DATATYPE_SHIFT[7:0] | RO | 0x00 | The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | ||
| 36 | [15:8] | USR_DATATYPE_TOTAL_BITS[7:0] | RO | 0x00 | The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | ||
| 37 | [7:0] | USR_DATATYPE_BITS[7:0] | RO | 0x00 | The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | ||
| 38 | 0x0109 | 0x0424 | REG_CHAN_USR_CNTRL_2 | ADC Interface Control & Status | |||
| 39 | [31:16] | USR_DECIMATION_M[15:0] | RW | 0x0000 | This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | ||
| 40 | [15:0] | USR_DECIMATION_N[15:0] | RW | 0x0000 | This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | ||
| 41 | 0x0110 | 0x0440 | REG_* | Channel 1, similar to register 0x100 to 0x10f. | |||
| 42 | 0x0120 | 0x0480 | REG_* | Channel 2, similar to register 0x100 to 0x10f. | |||
| 43 | 0x01F0 | 0x07c0 | REG_* | Channel 15, similar to register 0x100 to 0x10f. | |||
| 44 | Tue Mar 14 10:17:59 2023 |