143 lines
4.7 KiB
Verilog
143 lines
4.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_tdd_sync (
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// clock & reset
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clk,
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rst,
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// control signals
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sync_en, // synchronization enabled
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device_type, // master or slave
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sync_period, // periodicity of the sync pulse,
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enable_in, // tdd enable signal asserted by software
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enable_out, // synchronized tdd_enable
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// sync interface
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sync_out, // sync output for slave
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sync_in, // sync input
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resync // resync pulse for slave device
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);
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input clk;
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input rst;
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input sync_en;
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input device_type;
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input [31:0] sync_period;
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input enable_in;
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output enable_out;
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output sync_out;
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input sync_in;
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output resync;
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// internal registers
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reg enable_out = 1'b0;
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reg enable_synced = 1'b0;
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reg sync_in_d = 1'b0;
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reg sync_out = 1'b0;
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reg resync = 1'b0;
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reg [ 2:0] pulse_width = 3'h7;
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reg [31:0] pulse_counter = 32'h0;
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// the sync module can be bypassed
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always @(posedge clk) begin
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if (rst == 1) begin
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enable_out <= 1'b0;
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end else begin
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enable_out <= (sync_en) ? enable_synced : enable_in;
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end
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end
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// generate sync pulse
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always @(posedge clk) begin
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if(rst == 1) begin
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pulse_counter <= 0;
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pulse_width <= 3'h7;
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sync_out <= 1'h0;
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end else begin
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if (device_type == 1) begin
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pulse_counter <= (pulse_counter < sync_period) ? pulse_counter + 1 : 32'h0;
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if(pulse_counter == sync_period) begin
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sync_out <= enable_in;
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pulse_width <= 3'h0;
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end else begin
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pulse_width <= (pulse_width < 3'h7) ? pulse_width + 1 : pulse_width;
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sync_out <= (pulse_width == 3'h7) ? 0 : enable_in;
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end
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end
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end
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end
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// syncronize enalbe_in and generate resync for slave
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always @(posedge clk) begin
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sync_in_d <= sync_in;
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if(device_type == 1'b1) begin
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enable_synced <= enable_in;
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resync <= 1'b0;
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end else begin
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if (~sync_in_d & sync_in) begin
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enable_synced <= enable_in;
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resync <= 1'b1;
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end else begin
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resync <= 1'b0;
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end
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end
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end
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endmodule
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