12c95b059d
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic. This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced. |
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| .. | ||
| Makefile | ||
| axi_ad9361.v | ||
| axi_ad9361_alt_lvds_rx.v | ||
| axi_ad9361_alt_lvds_tx.v | ||
| axi_ad9361_constr.xdc | ||
| axi_ad9361_dev_if.v | ||
| axi_ad9361_dev_if_alt.v | ||
| axi_ad9361_hw.tcl | ||
| axi_ad9361_ip.tcl | ||
| axi_ad9361_rx.v | ||
| axi_ad9361_rx_channel.v | ||
| axi_ad9361_rx_pnmon.v | ||
| axi_ad9361_tdd.v | ||
| axi_ad9361_tdd_if.v | ||
| axi_ad9361_tx.v | ||
| axi_ad9361_tx_channel.v | ||