91 lines
3.3 KiB
Verilog
91 lines
3.3 KiB
Verilog
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// Copyright 2013(c) Analog Devices, Inc.
|
|
// Author: Lars-Peter Clausen <lars@metafoo.de>
|
|
//
|
|
// All rights reserved.
|
|
//
|
|
// Redistribution and use in source and binary forms, with or without modification,
|
|
// are permitted provided that the following conditions are met:
|
|
// - Redistributions of source code must retain the above copyright
|
|
// notice, this list of conditions and the following disclaimer.
|
|
// - Redistributions in binary form must reproduce the above copyright
|
|
// notice, this list of conditions and the following disclaimer in
|
|
// the documentation and/or other materials provided with the
|
|
// distribution.
|
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
|
// contributors may be used to endorse or promote products derived
|
|
// from this software without specific prior written permission.
|
|
// - The use of this software may or may not infringe the patent rights
|
|
// of one or more patent holders. This license does not release you
|
|
// from the requirement that you obtain separate licenses from these
|
|
// patent holders to use this software.
|
|
// - Use of the software either in source or binary form, must be run
|
|
// on or directly connected to an Analog Devices Inc. component.
|
|
//
|
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
//
|
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|
|
module dmac_response_generator (
|
|
input clk,
|
|
input resetn,
|
|
|
|
input enable,
|
|
output reg enabled,
|
|
|
|
input [ID_WIDTH-1:0] request_id,
|
|
output reg [ID_WIDTH-1:0] response_id,
|
|
input sync_id,
|
|
|
|
input eot,
|
|
|
|
output resp_valid,
|
|
input resp_ready,
|
|
output resp_eot,
|
|
output [1:0] resp_resp
|
|
);
|
|
|
|
parameter ID_WIDTH = 3;
|
|
|
|
`include "inc_id.h"
|
|
`include "resp.h"
|
|
|
|
assign resp_resp = RESP_OKAY;
|
|
assign resp_eot = eot;
|
|
|
|
assign resp_valid = request_id != response_id && enabled;
|
|
|
|
// We have to wait for all responses before we can disable the response handler
|
|
always @(posedge clk) begin
|
|
if (resetn == 1'b0) begin
|
|
enabled <= 1'b0;
|
|
end else begin
|
|
if (enable)
|
|
enabled <= 1'b1;
|
|
else if (request_id == response_id)
|
|
enabled <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (resetn == 1'b0) begin
|
|
response_id <= 'h0;
|
|
end else begin
|
|
if ((resp_valid && resp_ready) ||
|
|
(sync_id && response_id != request_id))
|
|
response_id <= inc_id(response_id);
|
|
end
|
|
end
|
|
|
|
endmodule
|