f232a36141
The paths from the HDMI interface registers to the IO pads are unconstrained. This means the P&R can in theory put the register anywhere which could lead to stability issues on the interface, depending on what else is in the fabric. To get predictable delays for the register to IO pad path place the register into the IOB section. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
hdl
Analog Devices HDL libraries and projects
Tools version:
- Vivado 2014.4.1
- Quartus 14.0
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: