f3142a6a7a
Use set_domain_assignment to set up the maximum pipeline stages for the main interconnect. |
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.. | ||
adi_board.tcl | ||
adi_env.tcl | ||
adi_make.tcl | ||
adi_make_boot_bin.tcl | ||
adi_project_intel.tcl | ||
adi_project_xilinx.tcl | ||
adi_tquest.tcl | ||
adi_xilinx_msg.tcl | ||
project-intel.mk | ||
project-toplevel.mk | ||
project-xilinx.mk |