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Rejeesh Kutty f3c41cd9aa common-base-designs: add intr net names 2015-03-12 15:55:50 -04:00
library utiil_gmii_to_rgmii: registerd Rx/ Tx paths. Changed RX clock buffers to a single BUFG 2015-03-12 16:57:52 +02:00
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README.md README: Add tools version 2015-01-06 10:24:06 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.2
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga