204 lines
5.8 KiB
Verilog
204 lines
5.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 1:0] ddr_dm,
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inout [15:0] ddr_dq,
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inout [ 1:0] ddr_dqs_n,
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inout [ 1:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [31:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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output tx_clk_out,
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output tx_frame_out,
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output [11:0] tx_data_out,
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output enable,
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output txnrx,
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input clk_out,
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inout gpio_resetb,
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inout gpio_en_agc,
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inout [ 3:0] gpio_ctl,
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inout [ 7:0] gpio_status,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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output pl_gpio0,
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input pl_gpio1,
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inout pl_gpio2,
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inout pl_gpio3,
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inout pl_gpio4
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);
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// internal signals
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wire [17:0] gpio_i;
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wire [17:0] gpio_o;
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wire [17:0] gpio_t;
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wire iic_scl;
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wire iic_sda;
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wire phaser_enable;
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wire pl_burst;
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wire pl_muxout;
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wire pl_spi_clk_o;
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wire pl_spi_miso;
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wire pl_spi_mosi;
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wire pl_txdata;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(14)
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) i_iobuf (
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.dio_t (gpio_t[13:0]),
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.dio_i (gpio_o[13:0]),
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.dio_o (gpio_i[13:0]),
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.dio_p ({ gpio_resetb, // 13:13
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gpio_en_agc, // 12:12
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gpio_ctl, // 11: 8
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gpio_status})); // 7: 0
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assign gpio_i[16:14] = gpio_o[16:14];
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assign gpio_i[17] = pl_muxout;
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assign phaser_enable = gpio_o[14];
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assign pl_gpio4 = iic_scl; //PL_GPIO4
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assign pl_gpio3 = iic_sda; //PL_GPIO3
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//PL_GPIO2
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_pl_gpio_iobuf (
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.dio_t (phaser_enable),
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.dio_i (pl_spi_clk_o),
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.dio_o (pl_muxout),
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.dio_p (pl_gpio2));
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//PL_GPIO1
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assign pl_spi_miso = pl_gpio1 & ~phaser_enable;
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assign pl_burst = pl_gpio1 & phaser_enable;
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//PL_GPIO0
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assign pl_gpio0 = phaser_enable ? pl_txdata : pl_spi_mosi;
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.rx_clk_in (rx_clk_in),
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.rx_data_in (rx_data_in),
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.rx_frame_in (rx_frame_in),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.spi_clk_i(1'b0),
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.spi_clk_o(pl_spi_clk_o),
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.spi_csn_i(1'b1),
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.spi_csn_o(),
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.spi_sdi_i(pl_spi_miso),
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.spi_sdo_i(1'b0),
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.spi_sdo_o(pl_spi_mosi),
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.tdd_ext_sync(pl_burst),
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.txdata_o(pl_txdata),
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.tx_clk_out (tx_clk_out),
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.tx_data_out (tx_data_out),
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.tx_frame_out (tx_frame_out),
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.txnrx (txnrx),
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.up_enable (gpio_o[15]),
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.up_txnrx (gpio_o[16]));
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endmodule
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