278 lines
15 KiB
Tcl
278 lines
15 KiB
Tcl
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# ad9144-xcvr
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add_instance avl_ad9144_xcvr avl_adxcvr 1.0
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set_instance_parameter_value avl_ad9144_xcvr {ID} {0}
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set_instance_parameter_value avl_ad9144_xcvr {TX_OR_RX_N} {1}
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set_instance_parameter_value avl_ad9144_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
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set_instance_parameter_value avl_ad9144_xcvr {LANE_RATE} {10000.0}
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set_instance_parameter_value avl_ad9144_xcvr {PLLCLK_FREQUENCY} {5000.0}
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set_instance_parameter_value avl_ad9144_xcvr {REFCLK_FREQUENCY} {500.0}
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set_instance_parameter_value avl_ad9144_xcvr {CORECLK_FREQUENCY} {250.0}
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set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_LANES} {4}
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set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_CONVS} {2}
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set_instance_parameter_value avl_ad9144_xcvr {FRM_BCNT} {1}
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set_instance_parameter_value avl_ad9144_xcvr {FRM_SCNT} {1}
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set_instance_parameter_value avl_ad9144_xcvr {MF_FCNT} {32}
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set_instance_parameter_value avl_ad9144_xcvr {HD} {1}
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add_connection sys_clk.clk avl_ad9144_xcvr.sys_clk
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add_connection sys_clk.clk_reset avl_ad9144_xcvr.sys_resetn
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add_interface tx_ref_clk clock sink
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set_interface_property tx_ref_clk EXPORT_OF avl_ad9144_xcvr.ref_clk
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add_interface tx_data_0 conduit end
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set_interface_property tx_data_0 EXPORT_OF avl_ad9144_xcvr.tx_data_0
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add_interface tx_data_1 conduit end
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set_interface_property tx_data_1 EXPORT_OF avl_ad9144_xcvr.tx_data_1
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add_interface tx_data_2 conduit end
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set_interface_property tx_data_2 EXPORT_OF avl_ad9144_xcvr.tx_data_2
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add_interface tx_data_3 conduit end
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set_interface_property tx_data_3 EXPORT_OF avl_ad9144_xcvr.tx_data_3
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add_interface tx_sysref conduit end
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set_interface_property tx_sysref EXPORT_OF avl_ad9144_xcvr.sysref
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add_interface tx_sync conduit end
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set_interface_property tx_sync EXPORT_OF avl_ad9144_xcvr.sync
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add_connection avl_ad9144_xcvr.tx_phy_s_0 avl_ad9144_xcvr.tx_ip_s_0
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add_connection avl_ad9144_xcvr.tx_phy_s_1 avl_ad9144_xcvr.tx_ip_s_3
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add_connection avl_ad9144_xcvr.tx_phy_s_2 avl_ad9144_xcvr.tx_ip_s_1
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add_connection avl_ad9144_xcvr.tx_phy_s_3 avl_ad9144_xcvr.tx_ip_s_2
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add_connection avl_ad9144_xcvr.tx_ip_d_0 avl_ad9144_xcvr.tx_phy_d_0
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add_connection avl_ad9144_xcvr.tx_ip_d_3 avl_ad9144_xcvr.tx_phy_d_1
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add_connection avl_ad9144_xcvr.tx_ip_d_1 avl_ad9144_xcvr.tx_phy_d_2
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add_connection avl_ad9144_xcvr.tx_ip_d_2 avl_ad9144_xcvr.tx_phy_d_3
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add_connection sys_cpu.data_master avl_ad9144_xcvr.core_pll_reconfig
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add_connection sys_cpu.data_master avl_ad9144_xcvr.lane_pll_reconfig
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add_connection sys_cpu.data_master avl_ad9144_xcvr.ip_reconfig
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# ad9144-xcvr
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add_instance axi_ad9144_xcvr axi_adxcvr 1.0
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set_instance_parameter_value axi_ad9144_xcvr {ID} {0}
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set_instance_parameter_value axi_ad9144_xcvr {TX_OR_RX_N} {1}
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set_instance_parameter_value axi_ad9144_xcvr {NUM_OF_LANES} {4}
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add_connection sys_clk.clk axi_ad9144_xcvr.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9144_xcvr.s_axi_reset
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add_connection axi_ad9144_xcvr.if_up_rst avl_ad9144_xcvr.rst
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add_connection avl_ad9144_xcvr.ready axi_ad9144_xcvr.ready
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add_connection axi_ad9144_xcvr.core_pll_locked avl_ad9144_xcvr.core_pll_locked
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add_connection sys_cpu.data_master axi_ad9144_xcvr.s_axi
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# ad9144-core
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add_instance axi_ad9144_core axi_ad9144 1.0
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set_instance_parameter_value axi_ad9144_core {QUAD_OR_DUAL_N} {0}
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add_connection avl_ad9144_xcvr.core_clk axi_ad9144_core.if_tx_clk
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add_connection axi_ad9144_core.if_tx_data avl_ad9144_xcvr.ip_data
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add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
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add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9144_core.s_axi
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# ad9144-unpack
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add_instance util_ad9144_upack util_upack 1.0
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set_instance_parameter_value util_ad9144_upack {CHANNEL_DATA_WIDTH} {64}
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set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2}
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add_connection avl_ad9144_xcvr.core_clk util_ad9144_upack.if_dac_clk
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add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0
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add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1
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# ad9144-dma
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add_instance axi_ad9144_dma axi_dmac 1.0
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set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_SRC} {128}
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set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_DEST} {128}
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set_instance_parameter_value axi_ad9144_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_DEST} {2}
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set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_SRC} {0}
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add_connection avl_ad9144_xcvr.core_clk axi_ad9144_dma.if_fifo_rd_clk
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add_connection util_ad9144_upack.if_dac_valid axi_ad9144_dma.if_fifo_rd_en
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add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout
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add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
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add_connection sys_clk.clk_reset axi_ad9144_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9144_dma.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9144_dma.s_axi
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9144_dma.m_src_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock
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add_connection axi_ad9144_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
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add_connection sys_cpu.irq axi_ad9144_dma.interrupt_sender
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# ad9680-xcvr
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add_instance avl_ad9680_xcvr avl_adxcvr 1.0
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set_instance_parameter_value avl_ad9680_xcvr {ID} {1}
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set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0}
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set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
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set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {10000.0}
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set_instance_parameter_value avl_ad9680_xcvr {PLLCLK_FREQUENCY} {5000.0}
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set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {500.0}
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set_instance_parameter_value avl_ad9680_xcvr {CORECLK_FREQUENCY} {250.0}
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set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4}
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set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2}
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set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1}
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set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1}
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set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32}
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set_instance_parameter_value avl_ad9680_xcvr {HD} {1}
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add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk
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add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn
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add_interface rx_ref_clk clock sink
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set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk
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add_interface rx_data_0 conduit end
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set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0
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add_interface rx_data_1 conduit end
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set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1
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add_interface rx_data_2 conduit end
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set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2
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add_interface rx_data_3 conduit end
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set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3
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add_interface rx_sysref conduit end
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set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
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add_interface rx_sync conduit end
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set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
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add_connection sys_cpu.data_master avl_ad9680_xcvr.core_pll_reconfig
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add_connection sys_cpu.data_master avl_ad9680_xcvr.ip_reconfig
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# ad9680-xcvr
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add_instance axi_ad9680_xcvr axi_adxcvr 1.0
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set_instance_parameter_value axi_ad9680_xcvr {ID} {1}
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set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0}
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set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4}
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add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset
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add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
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add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
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add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
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add_connection sys_cpu.data_master axi_ad9680_xcvr.s_axi
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# ad9680
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add_instance axi_ad9680_core axi_ad9680 1.0
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add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk
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add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof
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add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
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add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9680_core.s_axi
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# ad9680-pack
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add_instance util_ad9680_cpack util_cpack 1.0
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set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
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set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
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add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
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add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst
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add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk
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add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
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add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
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# ad9680-fifo
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add_instance ad9680_adcfifo util_adcfifo 1.0
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set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128}
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set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
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set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
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add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
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add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst
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add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk
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add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
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add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
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add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk
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# ad9680-dma
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add_instance axi_ad9680_dma axi_dmac 1.0
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set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128}
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set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128}
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set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
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set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk
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add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid
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add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data
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add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready
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add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
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add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
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add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
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add_connection sys_cpu.data_master axi_ad9680_dma.s_axi
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
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add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
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add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
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# reconfig sharing
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add_instance avl_adxcfg_0 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s1
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add_connection avl_adxcfg_0.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_0
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add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
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add_instance avl_adxcfg_1 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s1
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add_connection avl_adxcfg_1.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_1
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add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
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add_instance avl_adxcfg_2 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s1
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add_connection avl_adxcfg_2.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_2
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add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
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add_instance avl_adxcfg_3 avl_adxcfg 1.0
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add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
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add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s0
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add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s1
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add_connection avl_adxcfg_3.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_3
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add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
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# addresses
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set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.core_pll_reconfig baseAddress {0x10400000}
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set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.ip_reconfig baseAddress {0x10401000}
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set_connection_parameter_value sys_cpu.data_master/avl_ad9144_xcvr.lane_pll_reconfig baseAddress {0x10402000}
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set_connection_parameter_value sys_cpu.data_master/axi_ad9144_dma.s_axi baseAddress {0x1040c000}
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set_connection_parameter_value sys_cpu.data_master/axi_ad9144_xcvr.s_axi baseAddress {0x10410000}
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set_connection_parameter_value sys_cpu.data_master/axi_ad9144_core.s_axi baseAddress {0x10420000}
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set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.core_pll_reconfig baseAddress {0x10500000}
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set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.ip_reconfig baseAddress {0x10501000}
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set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi baseAddress {0x1050c000}
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set_connection_parameter_value sys_cpu.data_master/axi_ad9680_xcvr.s_axi baseAddress {0x10510000}
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set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi baseAddress {0x10520000}
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set_connection_parameter_value axi_ad9144_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
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set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s0 baseAddress {0x10404000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s0 baseAddress {0x10405000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s0 baseAddress {0x10406000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s0 baseAddress {0x10407000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s1 baseAddress {0x10504000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s1 baseAddress {0x10505000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s1 baseAddress {0x10506000}
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set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s1 baseAddress {0x10507000}
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# interrupts
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set_connection_parameter_value sys_cpu.irq/axi_ad9144_dma.interrupt_sender irqNumber {11}
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set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
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