168 lines
8.8 KiB
Tcl
168 lines
8.8 KiB
Tcl
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# fmcadc4
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir I rx_sysref
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create_bd_port -dir I -from 7 -to 0 rx_data_p
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create_bd_port -dir I -from 7 -to 0 rx_data_n
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# adc peripherals
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set axi_ad9680_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_0]
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set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0
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set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1]
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set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1
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set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd
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set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9680_cpack
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# adc common gt
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set axi_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc4_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc4_gt
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set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcadc4_gt
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set util_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc4_gt]
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set_property -dict [list CONFIG.QPLL_TX_OR_RX_N {0}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc4_gt
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_data]
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# connections (gt)
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ad_connect util_fmcadc4_gt/qpll_ref_clk rx_ref_clk
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ad_connect axi_fmcadc4_gt/gt_qpll_0 util_fmcadc4_gt/gt_qpll_0
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ad_connect axi_fmcadc4_gt/gt_qpll_1 util_fmcadc4_gt/gt_qpll_1
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ad_connect axi_fmcadc4_gt/gt_pll_0 util_fmcadc4_gt/gt_pll_0
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ad_connect axi_fmcadc4_gt/gt_pll_1 util_fmcadc4_gt/gt_pll_1
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ad_connect axi_fmcadc4_gt/gt_pll_2 util_fmcadc4_gt/gt_pll_2
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ad_connect axi_fmcadc4_gt/gt_pll_3 util_fmcadc4_gt/gt_pll_3
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ad_connect axi_fmcadc4_gt/gt_pll_4 util_fmcadc4_gt/gt_pll_4
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ad_connect axi_fmcadc4_gt/gt_pll_5 util_fmcadc4_gt/gt_pll_5
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ad_connect axi_fmcadc4_gt/gt_pll_6 util_fmcadc4_gt/gt_pll_6
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ad_connect axi_fmcadc4_gt/gt_pll_7 util_fmcadc4_gt/gt_pll_7
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ad_connect axi_fmcadc4_gt/gt_rx_0 util_fmcadc4_gt/gt_rx_0
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ad_connect axi_fmcadc4_gt/gt_rx_1 util_fmcadc4_gt/gt_rx_1
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ad_connect axi_fmcadc4_gt/gt_rx_2 util_fmcadc4_gt/gt_rx_2
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ad_connect axi_fmcadc4_gt/gt_rx_3 util_fmcadc4_gt/gt_rx_3
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ad_connect axi_fmcadc4_gt/gt_rx_4 util_fmcadc4_gt/gt_rx_4
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ad_connect axi_fmcadc4_gt/gt_rx_5 util_fmcadc4_gt/gt_rx_5
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ad_connect axi_fmcadc4_gt/gt_rx_6 util_fmcadc4_gt/gt_rx_6
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ad_connect axi_fmcadc4_gt/gt_rx_7 util_fmcadc4_gt/gt_rx_7
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ad_connect axi_fmcadc4_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_4 axi_ad9680_jesd/gt4_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_5 axi_ad9680_jesd/gt5_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_6 axi_ad9680_jesd/gt6_rx
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ad_connect axi_fmcadc4_gt/gt_rx_ip_7 axi_ad9680_jesd/gt7_rx
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_4 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_5 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_6 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_7 axi_ad9680_jesd/rxencommaalign_out
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# connections (adc)
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ad_connect util_fmcadc4_gt/rx_p rx_data_p
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ad_connect util_fmcadc4_gt/rx_n rx_data_n
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ad_connect util_fmcadc4_gt/rx_sysref rx_sysref
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ad_connect util_fmcadc4_gt/rx_sync rx_sync
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ad_connect util_fmcadc4_gt/rx_out_clk util_fmcadc4_gt/rx_clk
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
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ad_connect util_fmcadc4_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
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ad_connect util_fmcadc4_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
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ad_connect util_fmcadc4_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
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ad_connect util_fmcadc4_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
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ad_connect util_fmcadc4_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
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ad_connect util_fmcadc4_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
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ad_connect util_fmcadc4_gt/rx_data util_bsplit_rx_data/data
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_0/rx_clk
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_1/rx_clk
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ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data
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ad_connect util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_cpack/adc_clk
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ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_cpack/adc_rst
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ad_connect axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0
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ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0
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ad_connect axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0
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ad_connect axi_ad9680_core_0/adc_enable_1 axi_ad9680_cpack/adc_enable_1
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ad_connect axi_ad9680_core_0/adc_valid_1 axi_ad9680_cpack/adc_valid_1
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ad_connect axi_ad9680_core_0/adc_data_1 axi_ad9680_cpack/adc_data_1
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ad_connect axi_ad9680_core_1/adc_enable_0 axi_ad9680_cpack/adc_enable_2
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ad_connect axi_ad9680_core_1/adc_valid_0 axi_ad9680_cpack/adc_valid_2
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ad_connect axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2
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ad_connect axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3
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ad_connect axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3
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ad_connect axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3
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ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_fifo/adc_clk
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ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
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ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
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ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
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ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
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ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
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ad_connect axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_fmcadc4_gt
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ad_cpu_interconnect 0x44A00000 axi_ad9680_core_0
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ad_cpu_interconnect 0x44A10000 axi_ad9680_core_1
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ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_fmcadc4_gt/m_axi
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# interconnect (mem/adc)
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
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