AndreiGrozav f5ac0f7019 axi_logic_analyzer: equalize delay paths ... - Add parameter for input data delay time to easily match the one of the adc_trigger. - Change the trigger delay path to match between the internal and external(adc_trigger delays).		2019-09-13 11:55:11 +03:00
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Makefile	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
axi_logic_analyzer.v	axi_logic_analyzer: equalize delay paths	2019-09-13 11:55:11 +03:00
axi_logic_analyzer_constr.xdc	constraints: up_xfer_cntrl and up_xfer_status have its own constraints	2018-04-11 15:09:54 +03:00
axi_logic_analyzer_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
axi_logic_analyzer_reg.v	axi_logic_analyzer: Add module cascade support	2019-08-22 18:06:10 +03:00
axi_logic_analyzer_trigger.v	axi_logic_analyzer: equalize delay paths	2019-09-13 11:55:11 +03:00