5ec87615b0
The ready signal of the SYNC interface should be always 1'b1, regardless of ASYNC_SPI_VALUE. Drive the ready with one in both branches of the ASYNC_SPI_CLK generate block. |
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axi_spi_engine | ||
interfaces | ||
spi_engine_execution | ||
spi_engine_interconnect | ||
spi_engine_offload |