84a76b9dea
The ADV7511 samples the parallel data bus at the rising edge of sample clock. Generate the clock so that the falling edge is aligned to updating the bus data. This creates larger timing margins on each side of the sampling edge and makes the design more robust. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| common | ||
| zc706 | ||
| zed | ||
| Makefile | ||