28801f2f37
The DDR memory reference clock on the A10SoC development board is differential. Currently the EMIF core it is configured for single-ended configuration, which causes it to generate incorrect IOSTANDARD constraints. Those incorrect constraints get overwritten again in system_assign.tcl, so things are working, but this generates a warning when building the design Configure the EMIF core correctly and remove the manual constraint overwrite since they are no longer necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| a10soc_plddr4_assign.tcl | ||
| a10soc_plddr4_dacfifo_qsys.tcl | ||
| a10soc_system_assign.tcl | ||
| a10soc_system_qsys.tcl | ||