603 lines
19 KiB
Verilog
603 lines
19 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_adc_common #(
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// parameters
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parameter ID = 0,
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parameter [ 7:0] FPGA_TECHNOLOGY = 0,
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parameter [ 7:0] FPGA_FAMILY = 0,
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parameter [ 7:0] SPEED_GRADE = 0,
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parameter [ 7:0] DEV_PACKAGE = 0,
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parameter CONFIG = 0,
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parameter COMMON_ID = 6'h00,
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parameter DRP_DISABLE = 0,
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parameter USERPORTS_DISABLE = 0,
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parameter GPIO_DISABLE = 0,
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parameter START_CODE_DISABLE = 0
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) (
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// clock reset
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output mmcm_rst,
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// adc interface
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input adc_clk,
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output adc_rst,
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output adc_r1_mode,
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output adc_ddr_edgesel,
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output adc_pin_mode,
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input adc_status,
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input adc_sync_status,
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input adc_status_ovf,
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input [31:0] adc_clk_ratio,
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output [31:0] adc_start_code,
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output adc_sref_sync,
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output adc_sync,
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output adc_ext_sync_arm,
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output adc_ext_sync_disarm,
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output adc_ext_sync_manual_req,
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output [4:0] adc_num_lanes,
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output [7:0] adc_custom_control,
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output adc_crc_enable,
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output adc_sdr_ddr_n,
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output adc_symb_op,
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output adc_symb_8_16b,
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input [31:0] up_pps_rcounter,
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input up_pps_status,
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output reg up_pps_irq_mask,
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output reg up_adc_r1_mode = 'd0,
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// channel interface
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output up_adc_ce,
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input up_status_pn_err,
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input up_status_pn_oos,
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input up_status_or,
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// drp interface
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output up_drp_sel,
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output up_drp_wr,
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output [11:0] up_drp_addr,
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output [31:0] up_drp_wdata,
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input [31:0] up_drp_rdata,
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input up_drp_ready,
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input up_drp_locked,
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// ADC custom read/write interface
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output [31:0] adc_custom_wr,
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output adc_write_req,
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input [31:0] adc_custom_rd,
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input adc_read_valid,
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output adc_read_req,
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// user channel control
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output [ 7:0] up_usr_chanmax_out,
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input [ 7:0] up_usr_chanmax_in,
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input [31:0] up_adc_gpio_in,
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output [31:0] up_adc_gpio_out,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack
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);
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// parameters
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localparam VERSION = 32'h000a0262;
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// internal registers
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reg up_adc_clk_enb_int = 'd1;
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reg up_core_preset = 'd1;
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reg up_mmcm_preset = 'd1;
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reg up_wack_int = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_adc_clk_enb = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_resetn = 'd0;
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reg up_adc_sync = 'd0;
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reg up_adc_ext_sync_arm = 'd0;
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reg up_adc_ext_sync_disarm = 'd0;
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reg up_adc_ext_sync_manual_req = 'd0;
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reg up_adc_sref_sync = 'd0;
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reg [4:0] up_adc_num_lanes = 'd0;
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reg up_adc_sdr_ddr_n = 'd0;
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reg up_adc_symb_op = 'd0;
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reg up_adc_symb_8_16b = 'd0;
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reg up_adc_ddr_edgesel = 'd0;
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reg up_adc_pin_mode = 'd0;
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reg up_status_ovf = 'd0;
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reg [ 7:0] up_usr_chanmax_int = 'd0;
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reg [31:0] up_adc_start_code = 'd0;
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reg [31:0] up_adc_gpio_out_int = 'd0;
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reg [31:0] up_timer = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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reg [ 7:0] up_adc_custom_control = 'd0;
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reg up_adc_crc_enable = 'd0;
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reg [31:0] up_adc_custom_wr = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_rack_s;
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wire up_write_req;
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wire up_read_req;
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wire up_status_s;
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wire up_sync_status_s;
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wire up_status_ovf_s;
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wire up_cntrl_xfer_done_s;
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wire [31:0] up_adc_clk_count_s;
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wire up_drp_status_s;
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wire up_drp_rwn_s;
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wire [31:0] up_drp_rdata_hold_s;
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wire up_adc_read_valid;
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wire [31:0] up_adc_custom_rd;
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wire adc_rst_n;
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wire adc_rst_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:7] == {COMMON_ID,1'b0}) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:7] == {COMMON_ID,1'b0}) ? up_rreq : 1'b0;
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assign up_rack_s = (up_raddr[6:0] == 7'h21) ? up_adc_read_valid : up_rreq_s;
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assign up_write_req = (up_waddr[6:0] == 7'h20) ? up_wreq : 1'b0;
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assign up_read_req = (up_raddr[6:0] == 7'h21) ? up_rreq : 1'b0;
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// processor write interface
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assign up_wack = up_wack_int;
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assign up_adc_ce = up_adc_clk_enb_int;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_clk_enb_int <= 1'd1;
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up_core_preset <= 1'd1;
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up_mmcm_preset <= 1'd1;
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up_wack_int <= 'd0;
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up_scratch <= 'd0;
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up_adc_clk_enb <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_resetn <= 'd0;
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up_adc_sync <= 'd0;
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up_adc_ext_sync_arm <= 'd0;
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up_adc_ext_sync_disarm <= 'd0;
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up_adc_ext_sync_manual_req <= 'd0;
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up_adc_sref_sync <= 'd0;
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up_adc_num_lanes <= 'd0;
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up_adc_sdr_ddr_n <= 'd0;
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up_adc_symb_op <= 'd0;
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up_adc_symb_8_16b <= 'd0;
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up_adc_r1_mode <= 'd0;
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up_adc_ddr_edgesel <= 'd0;
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up_adc_pin_mode <= 'd0;
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up_pps_irq_mask <= 1'b1;
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up_adc_custom_control <= 'd0;
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up_adc_crc_enable <= 'd0;
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end else begin
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up_adc_clk_enb_int <= ~up_adc_clk_enb;
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up_core_preset <= ~up_resetn;
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_wack_int <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h04)) begin
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up_pps_irq_mask <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h10)) begin
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up_adc_clk_enb <= up_wdata[2];
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up_mmcm_resetn <= up_wdata[1];
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up_resetn <= up_wdata[0];
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end
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if (up_adc_sync == 1'b1) begin
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if (up_cntrl_xfer_done_s == 1'b1) begin
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up_adc_sync <= 1'b0;
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin
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up_adc_sync <= up_wdata[3];
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end
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if (up_adc_ext_sync_arm == 1'b1) begin
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if (up_cntrl_xfer_done_s == 1'b1) begin
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up_adc_ext_sync_arm <= 1'b0;
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin
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up_adc_ext_sync_arm <= up_wdata[1];
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end
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if (up_adc_ext_sync_disarm == 1'b1) begin
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if (up_cntrl_xfer_done_s == 1'b1) begin
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up_adc_ext_sync_disarm <= 1'b0;
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin
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up_adc_ext_sync_disarm <= up_wdata[2];
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end
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if (up_adc_ext_sync_manual_req == 1'b1) begin
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if (up_cntrl_xfer_done_s == 1'b1) begin
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up_adc_ext_sync_manual_req <= 1'b0;
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin
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up_adc_ext_sync_manual_req <= up_wdata[8];
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end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h13)) begin
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up_adc_crc_enable <= up_wdata[8];
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up_adc_custom_control <= up_wdata[7:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin
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up_adc_sdr_ddr_n <= up_wdata[16];
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up_adc_symb_op <= up_wdata[15];
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up_adc_symb_8_16b <= up_wdata[14];
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up_adc_num_lanes <= up_wdata[12:8];
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up_adc_sref_sync <= up_wdata[4];
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up_adc_r1_mode <= up_wdata[2];
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up_adc_ddr_edgesel <= up_wdata[1];
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up_adc_pin_mode <= up_wdata[0];
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end
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end
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end
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generate
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if (DRP_DISABLE == 1) begin
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assign up_drp_sel = 'd0;
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assign up_drp_wr = 'd0;
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assign up_drp_status_s = 'd0;
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assign up_drp_rwn_s = 'd0;
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assign up_drp_addr = 'd0;
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assign up_drp_wdata = 'd0;
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assign up_drp_rdata_hold_s = 'd0;
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end else begin
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reg up_drp_sel_int = 'd0;
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reg up_drp_wr_int = 'd0;
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reg up_drp_status_int = 'd0;
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reg up_drp_rwn_int = 'd0;
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reg [11:0] up_drp_addr_int = 'd0;
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reg [31:0] up_drp_wdata_int = 'd0;
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reg [31:0] up_drp_rdata_hold_int = 'd0;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_drp_sel_int <= 'd0;
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up_drp_wr_int <= 'd0;
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up_drp_status_int <= 'd0;
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up_drp_rwn_int <= 'd0;
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up_drp_addr_int <= 'd0;
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up_drp_wdata_int <= 'd0;
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up_drp_rdata_hold_int <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin
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up_drp_sel_int <= 1'b1;
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up_drp_wr_int <= ~up_wdata[28];
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end else begin
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up_drp_sel_int <= 1'b0;
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up_drp_wr_int <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin
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up_drp_status_int <= 1'b1;
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end else if (up_drp_ready == 1'b1) begin
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up_drp_status_int <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin
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up_drp_rwn_int <= up_wdata[28];
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up_drp_addr_int <= up_wdata[27:16];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1e)) begin
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up_drp_wdata_int <= up_wdata;
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end
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if (up_drp_ready == 1'b1) begin
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up_drp_rdata_hold_int <= up_drp_rdata;
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end
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end
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end
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assign up_drp_sel = up_drp_sel_int;
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assign up_drp_wr = up_drp_wr_int;
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assign up_drp_status_s = up_drp_status_int;
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assign up_drp_rwn_s = up_drp_rwn_int;
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assign up_drp_addr = up_drp_addr_int;
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assign up_drp_wdata = up_drp_wdata_int;
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assign up_drp_rdata_hold_s = up_drp_rdata_hold_int;
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end
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endgenerate
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_custom_wr <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h20)) begin
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up_adc_custom_wr <= up_wdata;
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end
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end
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end
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_ovf <= 'd0;
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end else begin
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if (up_status_ovf_s == 1'b1) begin
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up_status_ovf <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h22)) begin
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up_status_ovf <= up_status_ovf & ~up_wdata[2];
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end
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end
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end
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assign up_usr_chanmax_out = up_usr_chanmax_int;
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generate
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if (USERPORTS_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_usr_chanmax_int <= 'd0;
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end
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end else begin
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_usr_chanmax_int <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h28)) begin
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up_usr_chanmax_int <= up_wdata[7:0];
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end
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end
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end
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end
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endgenerate
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assign up_adc_gpio_out = up_adc_gpio_out_int;
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generate
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if (GPIO_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_adc_gpio_out_int <= 'd0;
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end
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end else begin
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_gpio_out_int <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h2f)) begin
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up_adc_gpio_out_int <= up_wdata;
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end
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end
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end
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end
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endgenerate
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generate
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if (START_CODE_DISABLE == 1) begin
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always @(posedge up_clk) begin
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up_adc_start_code <= 'd0;
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end
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end else begin
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_start_code <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h29)) begin
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up_adc_start_code <= up_wdata[31:0];
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end
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end
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end
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end
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endgenerate
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// timer with premature termination
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_timer <= 32'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h40)) begin
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up_timer <= up_wdata;
|
|
end else if (up_timer > 0) begin
|
|
up_timer <= up_timer - 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// processor read interface
|
|
|
|
assign up_rack = up_rack_int;
|
|
assign up_rdata = up_rdata_int;
|
|
|
|
always @(posedge up_clk) begin
|
|
if (up_rstn == 0) begin
|
|
up_rack_int <= 'd0;
|
|
up_rdata_int <= 'd0;
|
|
end else begin
|
|
up_rack_int <= up_rack_s;
|
|
if (up_rack_s == 1'b1) begin
|
|
case (up_raddr[6:0])
|
|
7'h00: up_rdata_int <= VERSION;
|
|
7'h01: up_rdata_int <= ID;
|
|
7'h02: up_rdata_int <= up_scratch;
|
|
7'h03: up_rdata_int <= CONFIG;
|
|
7'h04: up_rdata_int <= {31'b0, up_pps_irq_mask};
|
|
7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
|
|
7'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn};
|
|
7'h11: up_rdata_int <= {15'd0, up_adc_sdr_ddr_n,
|
|
up_adc_symb_op, up_adc_symb_8_16b,
|
|
1'd0, up_adc_num_lanes,
|
|
3'd0, up_adc_sref_sync,
|
|
up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
|
|
7'h12: up_rdata_int <= {20'd0,
|
|
3'b0, up_adc_ext_sync_manual_req,
|
|
4'b0,
|
|
1'b0, up_adc_ext_sync_disarm, up_adc_ext_sync_arm, 1'b0};
|
|
7'h13: up_rdata_int <= {23'd0, up_adc_crc_enable, up_adc_custom_control};
|
|
7'h15: up_rdata_int <= up_adc_clk_count_s;
|
|
7'h16: up_rdata_int <= adc_clk_ratio;
|
|
7'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
|
|
7'h1a: up_rdata_int <= {31'd0, up_sync_status_s};
|
|
7'h1c: up_rdata_int <= {3'd0, up_drp_rwn_s, up_drp_addr, 16'b0};
|
|
7'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
|
|
7'h1e: up_rdata_int <= up_drp_wdata;
|
|
7'h1f: up_rdata_int <= up_drp_rdata_hold_s;
|
|
7'h20: up_rdata_int <= up_adc_custom_wr;
|
|
7'h21: up_rdata_int <= up_adc_custom_rd;
|
|
7'h22: up_rdata_int <= {29'd0, up_status_ovf, 2'b0};
|
|
7'h23: up_rdata_int <= 32'd8;
|
|
7'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in};
|
|
7'h29: up_rdata_int <= up_adc_start_code;
|
|
7'h2e: up_rdata_int <= up_adc_gpio_in;
|
|
7'h2f: up_rdata_int <= up_adc_gpio_out_int;
|
|
7'h30: up_rdata_int <= up_pps_rcounter;
|
|
7'h31: up_rdata_int <= {31'b0, up_pps_status};
|
|
7'h40: up_rdata_int <= up_timer;
|
|
default: up_rdata_int <= 0;
|
|
endcase
|
|
end else begin
|
|
up_rdata_int <= 32'd0;
|
|
end
|
|
end
|
|
end
|
|
|
|
// resets
|
|
|
|
ad_rst i_mmcm_rst_reg (
|
|
.rst_async(up_mmcm_preset),
|
|
.clk(up_clk),
|
|
.rstn(),
|
|
.rst(mmcm_rst));
|
|
|
|
ad_rst i_core_rst_reg (
|
|
.rst_async(up_core_preset),
|
|
.clk(adc_clk),
|
|
.rstn(),
|
|
.rst(adc_rst_s));
|
|
|
|
// adc control & status
|
|
|
|
up_xfer_cntrl #(
|
|
.DATA_WIDTH(92)
|
|
) i_xfer_cntrl (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_data_cntrl ({ up_adc_sdr_ddr_n,
|
|
up_adc_symb_op,
|
|
up_adc_symb_8_16b,
|
|
up_adc_num_lanes,
|
|
up_adc_custom_control,
|
|
up_adc_crc_enable,
|
|
up_adc_sref_sync,
|
|
up_adc_ext_sync_arm,
|
|
up_adc_ext_sync_disarm,
|
|
up_adc_ext_sync_manual_req,
|
|
up_adc_sync,
|
|
up_write_req,
|
|
up_read_req,
|
|
up_adc_custom_wr,
|
|
up_adc_start_code,
|
|
up_adc_r1_mode,
|
|
up_adc_ddr_edgesel,
|
|
up_adc_pin_mode,
|
|
up_resetn}),
|
|
.up_xfer_done (up_cntrl_xfer_done_s),
|
|
.d_rst (adc_rst_s),
|
|
.d_clk (adc_clk),
|
|
.d_data_cntrl ({ adc_sdr_ddr_n,
|
|
adc_symb_op,
|
|
adc_symb_8_16b,
|
|
adc_num_lanes,
|
|
adc_custom_control,
|
|
adc_crc_enable,
|
|
adc_sref_sync,
|
|
adc_ext_sync_arm,
|
|
adc_ext_sync_disarm,
|
|
adc_ext_sync_manual_req,
|
|
adc_sync,
|
|
adc_write_req,
|
|
adc_read_req,
|
|
adc_custom_wr,
|
|
adc_start_code,
|
|
adc_r1_mode,
|
|
adc_ddr_edgesel,
|
|
adc_pin_mode,
|
|
adc_rst_n}));
|
|
|
|
// De-assert adc_rst together with an updated control set.
|
|
// This allows writing the control registers before releasing the reset.
|
|
// This is important at start-up when stable set of controls is required.
|
|
|
|
assign adc_rst = ~adc_rst_n;
|
|
|
|
up_xfer_status #(
|
|
.DATA_WIDTH(36)
|
|
) i_xfer_status (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_data_status ({up_sync_status_s,
|
|
up_status_s,
|
|
up_status_ovf_s,
|
|
up_adc_read_valid,
|
|
up_adc_custom_rd}),
|
|
.d_rst (adc_rst_s),
|
|
.d_clk (adc_clk),
|
|
.d_data_status ({ adc_sync_status,
|
|
adc_status,
|
|
adc_status_ovf,
|
|
adc_read_valid,
|
|
adc_custom_rd}));
|
|
|
|
// adc clock monitor
|
|
|
|
up_clock_mon i_clock_mon (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_d_count (up_adc_clk_count_s),
|
|
.d_rst (adc_rst_s),
|
|
.d_clk (adc_clk));
|
|
|
|
endmodule
|