208 lines
6.5 KiB
Verilog
208 lines
6.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_delay_cntrl #(
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// parameters
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parameter DISABLE = 0,
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parameter INIT_DELAY = 0,
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parameter DATA_WIDTH = 8,
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parameter DRP_WIDTH = 5,
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parameter BASE_ADDRESS = 6'h02
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) (
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// delay interface
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input delay_clk,
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output delay_rst,
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input delay_locked,
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// io interface
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output [(DATA_WIDTH-1):0] up_dld,
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output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata,
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input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack
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);
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generate
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if (DISABLE == 1) begin
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assign up_wack = 1'd0;
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assign up_rack = 1'd0;
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assign up_rdata = 32'd0;
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assign up_dld = 'd0;
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assign up_dwdata = 'd0;
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assign delay_rst = 1'd0;
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end else begin
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// internal registers
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reg up_preset = 'd0;
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reg up_wack_int = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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reg up_dlocked_m1 = 'd0;
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reg up_dlocked_m2 = 'd0;
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reg up_dlocked_m3 = 'd0;
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reg up_dlocked = 'd0;
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reg [(DATA_WIDTH-1):0] up_dld_int = 'd0;
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reg [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_int = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [ DRP_WIDTH-1:0] up_rdata_s;
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wire [(DATA_WIDTH-1):0] up_drdata4_s;
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wire [(DATA_WIDTH-1):0] up_drdata3_s;
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wire [(DATA_WIDTH-1):0] up_drdata2_s;
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wire [(DATA_WIDTH-1):0] up_drdata1_s;
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wire [(DATA_WIDTH-1):0] up_drdata0_s;
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wire [(DATA_WIDTH-1):0] up_dld_s;
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wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_s;
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wire [(DATA_WIDTH-1):0] up_dinit_s;
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wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dinitdata_s;
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wire delay_rst_s;
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// variables
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genvar n;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0;
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assign up_rdata_s = up_drdata >> (DRP_WIDTH*up_raddr[7:0]);
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// processor interface
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assign up_wack = up_wack_int;
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assign up_rack = up_rack_int;
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assign up_rdata = up_rdata_int;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_preset <= 1'd1;
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up_wack_int <= 'd0;
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up_rack_int <= 'd0;
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up_rdata_int <= 'd0;
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up_dlocked_m1 <= 'd0;
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up_dlocked_m2 <= 'd0;
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up_dlocked_m3 <= 'd0;
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up_dlocked <= 'd0;
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end else begin
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up_preset <= 1'd0;
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up_wack_int <= up_wreq_s;
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up_rack_int <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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if (up_dlocked == 1'b0) begin
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up_rdata_int <= 32'hffffffff;
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end else begin
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up_rdata_int <= {{32-DRP_WIDTH{1'b0}}, up_rdata_s};
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end
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end else begin
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up_rdata_int <= 32'd0;
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end
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up_dlocked_m1 <= delay_locked;
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up_dlocked_m2 <= up_dlocked_m1;
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up_dlocked_m3 <= up_dlocked_m2;
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up_dlocked <= up_dlocked_m3;
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end
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end
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// init delay values (after delay locked)
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dinit
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assign up_dinit_s[n] = up_dlocked_m2 & ~up_dlocked_m3;
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assign up_dinitdata_s[(n*DRP_WIDTH) +: DRP_WIDTH] = INIT_DELAY;
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end
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// write does not hold- read back what goes into effect.
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
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assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
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assign up_dwdata_s[(n*DRP_WIDTH) +: DRP_WIDTH] = (up_waddr[7:0] == n) ?
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up_wdata[DRP_WIDTH-1:0] : up_dwdata_int[(n*DRP_WIDTH) +: DRP_WIDTH];
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end
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assign up_dld = up_dld_int;
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assign up_dwdata = up_dwdata_int;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_dld_int <= 'd0;
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up_dwdata_int <= 'd0;
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end else begin
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up_dld_int <= up_dld_s | up_dinit_s;
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if ((up_dlocked_m2 == 1'b1) && (up_dlocked_m3 == 1'b0)) begin
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up_dwdata_int <= up_dinitdata_s;
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end else if (up_wreq_s == 1'b1) begin
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up_dwdata_int <= up_dwdata_s;
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end
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end
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end
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// resets
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assign delay_rst = delay_rst_s;
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ad_rst i_delay_rst_reg (
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.rst_async (up_preset),
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.clk (delay_clk),
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.rstn (),
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.rst (delay_rst_s));
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end
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endgenerate
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endmodule
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