290 lines
9.4 KiB
Verilog
290 lines
9.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_hdmi_rx #(
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parameter ID = 0
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) (
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// hdmi interface
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input hdmi_clk,
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output hdmi_rst,
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output hdmi_edge_sel,
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output hdmi_bgr,
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output hdmi_packed,
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output hdmi_csc_bypass,
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output [15:0] hdmi_vs_count,
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output [15:0] hdmi_hs_count,
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input hdmi_dma_ovf,
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input hdmi_dma_unf,
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input hdmi_tpm_oos,
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input hdmi_vs_oos,
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input hdmi_hs_oos,
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input hdmi_vs_mismatch,
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input hdmi_hs_mismatch,
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input [15:0] hdmi_vs,
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input [15:0] hdmi_hs,
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input [31:0] hdmi_clk_ratio,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack
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);
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localparam PCORE_VERSION = 32'h00040063;
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// internal registers
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reg up_core_preset = 'd0;
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reg up_resetn = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_edge_sel = 'd0;
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reg up_bgr = 'd0;
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reg up_packed = 'd0;
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reg up_csc_bypass = 'd0;
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reg up_dma_ovf = 'd0;
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reg up_dma_unf = 'd0;
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reg up_tpm_oos = 'd0;
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reg up_vs_oos = 'd0;
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reg up_hs_oos = 'd0;
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reg up_vs_mismatch = 'd0;
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reg up_hs_mismatch = 'd0;
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reg [15:0] up_vs_count = 'd0;
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reg [15:0] up_hs_count = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_dma_ovf_s;
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wire up_dma_unf_s;
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wire up_vs_oos_s;
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wire up_hs_oos_s;
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wire up_vs_mismatch_s;
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wire up_hs_mismatch_s;
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wire [15:0] up_vs_s;
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wire [15:0] up_hs_s;
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wire [31:0] up_clk_count_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_core_preset <= 1'd1;
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up_resetn <= 'd0;
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_edge_sel <= 'd0;
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up_bgr <= 'd0;
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up_packed <= 'd0;
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up_csc_bypass <= 'd0;
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up_dma_ovf <= 'd0;
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up_dma_unf <= 'd0;
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up_tpm_oos <= 'd0;
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up_vs_oos <= 'd0;
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up_hs_oos <= 'd0;
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up_vs_mismatch <= 'd0;
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up_hs_mismatch <= 'd0;
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up_vs_count <= 'd0;
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up_hs_count <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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up_core_preset <= ~up_resetn;
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
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up_resetn <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
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up_edge_sel <= up_wdata[3];
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up_bgr <= up_wdata[2];
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up_packed <= up_wdata[1];
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up_csc_bypass <= up_wdata[0];
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end
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if (up_dma_ovf_s == 1'b1) begin
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up_dma_ovf <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
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up_dma_ovf <= up_dma_ovf & ~up_wdata[1];
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end
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if (up_dma_unf_s == 1'b1) begin
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up_dma_unf <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
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up_dma_unf <= up_dma_unf & ~up_wdata[0];
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end
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if (up_tpm_oos_s == 1'b1) begin
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up_tpm_oos <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
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up_tpm_oos <= up_tpm_oos & ~up_wdata[1];
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end
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if (up_vs_oos_s == 1'b1) begin
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up_vs_oos <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
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up_vs_oos <= up_vs_oos & ~up_wdata[3];
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end
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if (up_hs_oos_s == 1'b1) begin
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up_hs_oos <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
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up_hs_oos <= up_hs_oos & ~up_wdata[2];
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end
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if (up_vs_mismatch_s == 1'b1) begin
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up_vs_mismatch <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
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up_vs_mismatch <= up_vs_mismatch & ~up_wdata[1];
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end
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if (up_hs_mismatch_s == 1'b1) begin
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up_hs_mismatch <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
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up_hs_mismatch <= up_hs_mismatch & ~up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
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up_vs_count <= up_wdata[31:16];
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up_hs_count <= up_wdata[15:0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if(up_rreq_s == 1'b1) begin
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case (up_raddr[11:0])
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12'h000: up_rdata <= PCORE_VERSION;
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12'h001: up_rdata <= ID;
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12'h002: up_rdata <= up_scratch;
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12'h010: up_rdata <= {31'h0, up_resetn};
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12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass};
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12'h015: up_rdata <= up_clk_count_s;
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12'h016: up_rdata <= hdmi_clk_ratio;
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12'h018: up_rdata <= {30'h0, up_dma_ovf, up_dma_unf};
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12'h019: up_rdata <= {30'h0, up_tpm_oos, 1'b0};
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12'h020: up_rdata <= {28'h0, up_vs_oos, up_hs_oos,
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up_vs_mismatch, up_hs_mismatch};
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12'h100: up_rdata <= {up_vs_count, up_hs_count};
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12'h101: up_rdata <= {up_vs_s, up_hs_s};
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default: up_rdata <= 0;
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endcase
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end
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end
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end
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// resets
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ad_rst i_hdmi_rst_reg (
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.rst_async (up_core_preset),
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.clk (hdmi_clk),
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.rstn (),
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.rst (hdmi_rst));
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// hdmi control & status
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up_xfer_cntrl #(
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.DATA_WIDTH(36)
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) i_hdmi_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_edge_sel,
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up_bgr,
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up_packed,
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up_csc_bypass,
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up_vs_count,
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up_hs_count}),
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.up_xfer_done (),
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.d_rst (hdmi_rst),
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.d_clk (hdmi_clk),
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.d_data_cntrl ({ hdmi_edge_sel,
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hdmi_bgr,
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hdmi_packed,
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hdmi_csc_bypass,
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hdmi_vs_count,
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hdmi_hs_count}));
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up_xfer_status #(
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.DATA_WIDTH(39)
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) i_hdmi_xfer_status (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_status ({ up_dma_ovf_s,
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up_dma_unf_s,
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up_tpm_oos_s,
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up_vs_oos_s,
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up_hs_oos_s,
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up_vs_mismatch_s,
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up_hs_mismatch_s,
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up_vs_s,
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up_hs_s}),
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.d_rst (hdmi_rst),
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.d_clk (hdmi_clk),
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.d_data_status ({ hdmi_dma_ovf,
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hdmi_dma_unf,
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hdmi_tpm_oos,
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hdmi_vs_oos,
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hdmi_hs_oos,
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hdmi_vs_mismatch,
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hdmi_hs_mismatch,
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hdmi_vs,
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hdmi_hs}));
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up_clock_mon i_hdmi_clock_mon (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_d_count (up_clk_count_s),
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.d_rst (hdmi_rst),
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.d_clk (hdmi_clk));
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endmodule
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