120 lines
4.8 KiB
Tcl
120 lines
4.8 KiB
Tcl
#
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# Parameter description:
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# RX_JESD_L : Number of lanes per link
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#
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# JESD204B interface configuration parameters
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L)
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set RX_NUM_OF_CONVERTERS 2
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set RX_SAMPLES_PER_FRAME 1
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set RX_SAMPLE_WIDTH 16
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set RX_SAMPLES_PER_CHANNEL [expr ($RX_NUM_OF_LANES*32) / ($RX_NUM_OF_CONVERTERS*$RX_SAMPLE_WIDTH)] ; # (L * 32) / (M * N)
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set MAX_RX_NUM_OF_LANES 2
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_ad6676_xcvr
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ad_ip_parameter axi_ad6676_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_ad6676_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad6676_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_ad6676_xcvr CONFIG.LPM_OR_DFE_N 0
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ad_ip_parameter axi_ad6676_xcvr CONFIG.SYS_CLK_SEL 0x0
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ad_ip_parameter axi_ad6676_xcvr CONFIG.OUT_CLK_SEL 0x4
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adi_axi_jesd204_rx_create axi_ad6676_jesd $RX_NUM_OF_LANES
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adi_tpl_jesd204_rx_create axi_ad6676_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH \
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ad_ip_instance util_cpack2 axi_ad6676_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac axi_ad6676_dma
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ad_ip_parameter axi_ad6676_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_ad6676_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad6676_dma CONFIG.ID 0
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ad_ip_parameter axi_ad6676_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad6676_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad6676_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_ad6676_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad6676_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad6676_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad6676_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad6676_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# transceiver core
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ad_ip_instance util_adxcvr util_ad6676_xcvr
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ad_ip_parameter util_ad6676_xcvr CONFIG.CPLL_FBDIV 2
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ad_ip_parameter util_ad6676_xcvr CONFIG.CPLL_FBDIV_4_5 5
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ad_ip_parameter util_ad6676_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_parameter util_ad6676_xcvr CONFIG.RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES
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ad_ip_parameter util_ad6676_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_parameter util_ad6676_xcvr CONFIG.RX_CLK25_DIV 8
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ad_ip_parameter util_ad6676_xcvr CONFIG.RX_DFE_LPM_CFG 0x0954
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ad_ip_parameter util_ad6676_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020
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# reference clocks & resets
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create_bd_port -dir I rx_ref_clk_0
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create_bd_port -dir O rx_core_clk
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ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_cpll_rst_*
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ad_connect $sys_cpu_resetn util_ad6676_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_ad6676_xcvr/up_clk
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# connections (adc)
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ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd {} {} {} $MAX_RX_NUM_OF_LANES
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ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/link_clk
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ad_connect util_ad6676_xcvr/rx_out_clk_0 rx_core_clk
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ad_connect axi_ad6676_jesd/rx_sof axi_ad6676_core/link_sof
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ad_connect axi_ad6676_jesd/rx_data_tdata axi_ad6676_core/link_data
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ad_connect axi_ad6676_jesd/rx_data_tvalid axi_ad6676_core/link_valid
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ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/clk
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ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/reset
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ad_connect axi_ad6676_core/adc_dovf axi_ad6676_cpack/fifo_wr_overflow
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ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/fifo_wr_en
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect axi_ad6676_core/adc_enable_${i} axi_ad6676_cpack/enable_${i}
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ad_connect axi_ad6676_core/adc_data_${i} axi_ad6676_cpack/fifo_wr_data_${i}
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}
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ad_connect axi_ad6676_core/link_clk axi_ad6676_dma/fifo_wr_clk
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ad_connect axi_ad6676_dma/fifo_wr axi_ad6676_cpack/packed_fifo_wr
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad6676_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad6676_core
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ad_cpu_interconnect 0x44AA0000 axi_ad6676_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad6676_dma
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# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_cpu_clk axi_ad6676_xcvr/m_axi
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# interconnect (adc)
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk axi_ad6676_dma/m_dest_axi
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ad_connect $sys_dma_resetn axi_ad6676_dma/m_dest_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-12 mb-12 axi_ad6676_jesd/irq
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ad_cpu_interrupt ps-13 mb-13 axi_ad6676_dma/irq
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