150 lines
4.3 KiB
Verilog
Executable File
150 lines
4.3 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output ddr4_act_n,
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output [16:0] ddr4_addr,
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output [ 1:0] ddr4_ba,
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output ddr4_bg,
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output ddr4_ck_p,
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output ddr4_ck_n,
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output ddr4_cke,
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output ddr4_cs_n,
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inout [ 7:0] ddr4_dm_n,
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inout [63:0] ddr4_dq,
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inout [ 7:0] ddr4_dqs_p,
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inout [ 7:0] ddr4_dqs_n,
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output ddr4_odt,
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output ddr4_reset_n,
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output mdio_mdc,
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inout mdio_mdio,
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input phy_clk_p,
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input phy_clk_n,
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output phy_rst_n,
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input phy_rx_p,
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input phy_rx_n,
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output phy_tx_p,
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output phy_tx_n,
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inout [16:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda
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);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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assign gpio_i[63:32] = gpio_o[63:32];
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assign gpio_i[31:18] = gpio_o[31:18];
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assign iic_rstn = 1'b1;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH (17)
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) i_iobuf_bd (
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.dio_t (gpio_t[16:0]),
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.dio_i (gpio_o[16:0]),
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.dio_o (gpio_i[16:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.sys_rst (sys_rst),
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.sys_clk_clk_n (sys_clk_n),
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.sys_clk_clk_p (sys_clk_p),
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.ddr4_act_n (ddr4_act_n),
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.ddr4_adr (ddr4_addr),
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.ddr4_ba (ddr4_ba),
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.ddr4_bg (ddr4_bg),
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.ddr4_ck_c (ddr4_ck_n),
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.ddr4_ck_t (ddr4_ck_p),
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.ddr4_cke (ddr4_cke),
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.ddr4_cs_n (ddr4_cs_n),
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.ddr4_dm_n (ddr4_dm_n),
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.ddr4_dq (ddr4_dq),
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.ddr4_dqs_c (ddr4_dqs_n),
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.ddr4_dqs_t (ddr4_dqs_p),
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.ddr4_odt (ddr4_odt),
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.ddr4_reset_n (ddr4_reset_n),
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.phy_sd (1'b1),
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.phy_rst_n (phy_rst_n),
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.sgmii_rxn (phy_rx_n),
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.sgmii_rxp (phy_rx_p),
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.sgmii_txn (phy_tx_n),
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.sgmii_txp (phy_tx_p),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.sgmii_phyclk_clk_n (phy_clk_n),
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.sgmii_phyclk_clk_p (phy_clk_p),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.spi_clk_i (),
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.spi_clk_o (),
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.spi_csn_i (1'b1),
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.spi_csn_o (1'b1),
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.spi_sdi_i (1'b0),
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.spi_sdo_i (),
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.spi_sdo_o (),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]));
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endmodule
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