243 lines
7.8 KiB
Verilog
243 lines
7.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adcfifo #(
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parameter ADC_DATA_WIDTH = 128,
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parameter DMA_DATA_WIDTH = 64,
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parameter AXI_DATA_WIDTH = 512,
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parameter DMA_READY_ENABLE = 1,
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parameter AXI_SIZE = 2,
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parameter AXI_LENGTH = 16,
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parameter AXI_ADDRESS = 32'h00000000,
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parameter AXI_ADDRESS_LIMIT = 32'hffffffff
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) (
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// fifo interface
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input adc_rst,
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input adc_clk,
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input adc_wr,
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input [ADC_DATA_WIDTH-1:0] adc_wdata,
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output adc_wovf,
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// dma interface
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input dma_clk,
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output dma_wr,
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output [DMA_DATA_WIDTH-1:0] dma_wdata,
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input dma_wready,
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input dma_xfer_req,
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output [ 3:0] dma_xfer_status,
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// axi interface
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input axi_clk,
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input axi_resetn,
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output axi_awvalid,
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output [ 3:0] axi_awid,
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output [ 1:0] axi_awburst,
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output axi_awlock,
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output [ 3:0] axi_awcache,
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output [ 2:0] axi_awprot,
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output [ 3:0] axi_awqos,
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output [ 3:0] axi_awuser,
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output [ 7:0] axi_awlen,
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output [ 2:0] axi_awsize,
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output [ 31:0] axi_awaddr,
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input axi_awready,
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output axi_wvalid,
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output [AXI_DATA_WIDTH-1:0] axi_wdata,
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output [(AXI_DATA_WIDTH/8)-1:0] axi_wstrb,
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output axi_wlast,
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output [ 3:0] axi_wuser,
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input axi_wready,
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input axi_bvalid,
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input [ 3:0] axi_bid,
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input [ 1:0] axi_bresp,
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input [ 3:0] axi_buser,
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output axi_bready,
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output axi_arvalid,
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output [ 3:0] axi_arid,
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output [ 1:0] axi_arburst,
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output axi_arlock,
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output [ 3:0] axi_arcache,
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output [ 2:0] axi_arprot,
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output [ 3:0] axi_arqos,
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output [ 3:0] axi_aruser,
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output [ 7:0] axi_arlen,
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output [ 2:0] axi_arsize,
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output [ 31:0] axi_araddr,
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input axi_arready,
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input axi_rvalid,
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input [ 3:0] axi_rid,
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input [ 3:0] axi_ruser,
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input [ 1:0] axi_rresp,
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input axi_rlast,
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input [AXI_DATA_WIDTH-1:0] axi_rdata,
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output axi_rready
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);
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// internal signals
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wire adc_dwr_s;
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wire [AXI_DATA_WIDTH-1:0] adc_ddata_s;
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wire axi_rd_req_s;
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wire [ 31:0] axi_rd_addr_s;
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wire [ 3:0] axi_xfer_status_s;
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wire axi_drst_s;
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wire axi_dvalid_s;
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wire [AXI_DATA_WIDTH-1:0] axi_ddata_s;
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wire axi_dready_s;
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// instantiations
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axi_adcfifo_adc #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.ADC_DATA_WIDTH (ADC_DATA_WIDTH)
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) i_adc_if (
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.adc_rst (adc_rst),
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.adc_clk (adc_clk),
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.adc_wr (adc_wr),
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.adc_wdata (adc_wdata),
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.adc_wovf (adc_wovf),
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.adc_dwr (adc_dwr_s),
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.adc_ddata (adc_ddata_s),
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.axi_drst (axi_drst_s),
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.axi_clk (axi_clk),
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.axi_xfer_status (axi_xfer_status_s));
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axi_adcfifo_wr #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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.AXI_ADDRESS (AXI_ADDRESS),
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.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
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) i_wr (
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.dma_xfer_req (dma_xfer_req),
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.axi_rd_req (axi_rd_req_s),
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.axi_rd_addr (axi_rd_addr_s),
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.adc_rst (adc_rst),
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.adc_clk (adc_clk),
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.adc_wr (adc_dwr_s),
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.adc_wdata (adc_ddata_s),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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.axi_awvalid (axi_awvalid),
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.axi_awid (axi_awid),
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.axi_awburst (axi_awburst),
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.axi_awlock (axi_awlock),
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.axi_awcache (axi_awcache),
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.axi_awprot (axi_awprot),
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.axi_awqos (axi_awqos),
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.axi_awuser (axi_awuser),
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.axi_awlen (axi_awlen),
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.axi_awsize (axi_awsize),
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.axi_awaddr (axi_awaddr),
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.axi_awready (axi_awready),
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.axi_wvalid (axi_wvalid),
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.axi_wdata (axi_wdata),
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.axi_wstrb (axi_wstrb),
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.axi_wlast (axi_wlast),
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.axi_wuser (axi_wuser),
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.axi_wready (axi_wready),
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.axi_bvalid (axi_bvalid),
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.axi_bid (axi_bid),
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.axi_bresp (axi_bresp),
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.axi_buser (axi_buser),
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.axi_bready (axi_bready),
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.axi_dwovf (axi_xfer_status_s[0]),
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.axi_dwunf (axi_xfer_status_s[1]),
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.axi_werror (axi_xfer_status_s[2]));
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axi_adcfifo_rd #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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.AXI_ADDRESS (AXI_ADDRESS),
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.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
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) i_rd (
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.dma_xfer_req (dma_xfer_req),
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.axi_rd_req (axi_rd_req_s),
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.axi_rd_addr (axi_rd_addr_s),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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.axi_arvalid (axi_arvalid),
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.axi_arid (axi_arid),
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.axi_arburst (axi_arburst),
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.axi_arlock (axi_arlock),
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.axi_arcache (axi_arcache),
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.axi_arprot (axi_arprot),
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.axi_arqos (axi_arqos),
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.axi_aruser (axi_aruser),
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.axi_arlen (axi_arlen),
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.axi_arsize (axi_arsize),
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.axi_araddr (axi_araddr),
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.axi_arready (axi_arready),
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.axi_rvalid (axi_rvalid),
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.axi_rid (axi_rid),
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.axi_ruser (axi_ruser),
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.axi_rresp (axi_rresp),
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.axi_rlast (axi_rlast),
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.axi_rdata (axi_rdata),
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.axi_rready (axi_rready),
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.axi_rerror (axi_xfer_status_s[3]),
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.axi_drst (axi_drst_s),
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.axi_dvalid (axi_dvalid_s),
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.axi_ddata (axi_ddata_s),
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.axi_dready (axi_dready_s));
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axi_adcfifo_dma #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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.DMA_READY_ENABLE (DMA_READY_ENABLE)
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) i_dma_if (
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.axi_clk (axi_clk),
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.axi_drst (axi_drst_s),
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.axi_dvalid (axi_dvalid_s),
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.axi_ddata (axi_ddata_s),
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.axi_dready (axi_dready_s),
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.axi_xfer_status (axi_xfer_status_s),
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.dma_clk (dma_clk),
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.dma_wr (dma_wr),
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.dma_wdata (dma_wdata),
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.dma_wready (dma_wready),
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.dma_xfer_req (dma_xfer_req),
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.dma_xfer_status (dma_xfer_status));
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endmodule
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