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Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy 
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 		2022-05-27 00:48:34 +03:00
..
common ad_quadmxfe1_ebz: Refactor MxFE GPIOs 2022-05-11 18:09:08 +03:00
vcu118 ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy 2022-05-27 00:48:34 +03:00
Makefile ad_quadmxfe1_ebz: Initial version 2021-11-10 14:03:34 +02:00
Readme.md ad_quadmxfe1_ebz : Add readme file 2021-11-12 14:08:56 +02:00

Readme.md

QUAD-MxFE Platform HDL Project

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