pluto_hdl_adi/library/axi_dmac/tb
Lars-Peter Clausen 8937c365a0 axi_dmac: Hook up rlast for MM-AXI source interface
For the memory-mapped AXI read interface the slave asserts rlast for the
last beat in a burst.

This means we don't have to count the number of beats to know when the
burst is completed but instead can use rlast. This slightly reduces the
amount of resources needed for the MM-AXI source module and given that the
beat_counter is often the bottleneck timing wise this should also improve
the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
..
axi_read_slave.v axi_dmac: Add transfer testbenches 2018-05-03 14:49:06 +02:00
axi_slave.v axi_dmac: Add transfer testbenches 2018-05-03 14:49:06 +02:00
axi_write_slave.v axi_dmac/dma_write_tb: added data integrity check 2018-05-03 14:49:06 +02:00
dma_read_shutdown_tb axi_dmac: Add testbenches that exercise DMA shutdown 2018-07-03 13:44:34 +02:00
dma_read_shutdown_tb.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
dma_read_tb axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
dma_read_tb.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
dma_write_shutdown_tb axi_dmac: Add testbenches that exercise DMA shutdown 2018-07-03 13:44:34 +02:00
dma_write_shutdown_tb.v axi_dmac: Add testbenches that exercise DMA shutdown 2018-07-03 13:44:34 +02:00
dma_write_tb axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
dma_write_tb.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
regmap_tb axi_dmac: Add simple register map testbench 2018-05-03 14:49:06 +02:00
regmap_tb.v axi_dmac: made vlog pass 2018-05-03 14:49:06 +02:00
reset_manager_tb axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
reset_manager_tb.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
run_tb.sh axi_dmac: added ModelSim support to run_tb.sh 2018-05-03 14:49:06 +02:00
tb_base.v axi_dmac: Add simple register map testbench 2018-05-03 14:49:06 +02:00