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Lars-Peter Clausen 69a23ecde3 avl_adxcvr: Simplify TX lane mapping 
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.

Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.

The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.

In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.

This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-08-03 17:57:58 +02:00
..
ad5766_sdz scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad6676evb Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
ad7616_sdz scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad7768evb scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9265_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9434_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9467_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9739a_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad77681evb library- remove ad_cmos_* 2017-07-26 10:20:39 -04:00
adaq7980_sdz scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
adrv9361z7035 axi_ad9361: Update the PPS receiver module 2017-08-02 16:38:23 +01:00
adrv9364z7020 axi_ad9361: Update the PPS receiver module 2017-08-02 16:38:23 +01:00
adrv9371x avl_adxcvr: Simplify TX lane mapping 2017-08-03 17:57:58 +02:00
adv7511 Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
arradio arradio- remove dma_xfer_in from upack 2017-07-28 16:19:24 -04:00
cftl_cip scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
cftl_std scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
cn0363 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
common Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
daq1 hdlmake.pl updates 2017-07-31 09:02:12 -04:00
daq2 avl_adxcvr: Simplify TX lane mapping 2017-08-03 17:57:58 +02:00
daq3 avl_adxcvr: Simplify TX lane mapping 2017-08-03 17:57:58 +02:00
fmcadc2 hdlmake.pl- remove ad_lvds 2017-07-26 10:32:44 -04:00
fmcadc4 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
fmcadc5 hdlmake.pl- remove ad_lvds 2017-07-26 10:32:44 -04:00
fmcjesdadc1 avl_adxcvr: Derive PLL and core clock frequency from lane rate 2017-07-28 15:11:08 +02:00
fmcomms2 Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
fmcomms5 Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
fmcomms7 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
fmcomms11 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
imageon scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
m2k m2k: Enable correction for the interpolation module 2017-08-03 17:24:26 +03:00
motcon2_fmc Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
pluto scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
scripts adi_project_alt.tcl: Disable a few warnings generated by standard components 2017-08-01 15:18:40 +02:00
usb_fx3 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
usdrx1 avl_adxcvr: Derive PLL and core clock frequency from lane rate 2017-07-28 15:11:08 +02:00
usrpe31x scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Makefile hdlmake.pl updates 2017-06-15 11:42:44 -04:00