pluto_hdl_adi/projects/daq3
Lars-Peter Clausen 69a23ecde3 avl_adxcvr: Simplify TX lane mapping
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.

Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.

The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.

In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.

This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
..
a10gx hdlmake.pl - updates 2017-06-07 10:23:20 -04:00
common avl_adxcvr: Simplify TX lane mapping 2017-08-03 17:57:58 +02:00
kcu105 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
zc706 daq3/zc706: Fix system_top instantiation 2017-07-06 13:29:09 +01:00
zcu102 hdlmake.pl updates 2017-07-31 09:02:12 -04:00
Makefile hdlmake.pl updates 2017-07-31 09:02:12 -04:00