| .. |
|
ad_cmos_clk.v
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
ad_cmos_in.v
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
ad_cmos_out.v
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
ad_iobuf.v
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
ad_lvds_clk.v
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
ad_lvds_in.v
|
ad_lvds_in: Allow to disable IDELAY
|
2017-04-18 12:17:39 +02:00 |
|
ad_lvds_out.v
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
ad_mmcm_drp.v
|
ad_mmcm_drp: Fix generate block
|
2017-04-20 18:43:37 +03:00 |
|
ad_mul.v
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
ad_rst_constr.xdc
|
restructure: Move xilinx specific constraints to /library/xilinx/common/
|
2017-03-30 16:16:02 +03:00 |
|
ad_serdes_clk.v
|
ad_serdes_clk: Fix generate block
|
2017-04-20 18:49:00 +03:00 |
|
ad_serdes_in.v
|
ad_serdes: SERDES_FACTOR handover missing
|
2016-10-10 16:38:42 +03:00 |
|
ad_serdes_out.v
|
ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data
|
2017-04-18 12:17:39 +02:00 |
|
up_clock_mon_constr.xdc
|
restructure: Move xilinx specific constraints to /library/xilinx/common/
|
2017-03-30 16:16:02 +03:00 |
|
up_xfer_cntrl_constr.xdc
|
restructure: Move xilinx specific constraints to /library/xilinx/common/
|
2017-03-30 16:16:02 +03:00 |
|
up_xfer_status_constr.xdc
|
restructure: Move xilinx specific constraints to /library/xilinx/common/
|
2017-03-30 16:16:02 +03:00 |
faa5e3d667