90 lines
3.4 KiB
Verilog
90 lines
3.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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//
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// Pack two input beats into one and align it based on start of frame
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//
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// Frame size 2 beats:
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// Temporal ordering of input:
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// idata : MS Beat, LS Beat, MS Beat, LS Beat, ...
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// sof : 1, 0, 1, 0, ...
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// Format of output beats: {MS Beat, LS Beat}
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//
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// Frame size 4 beats:
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// Temporal ordering of input:
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// idata : MS Beat, LS Beat, MS Beat, LS Beat, MS Beat, LS Beat, ...
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// sof : 1, 0, 0, 0, 1, 0, ...
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module adrv9001_pack #(
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parameter WIDTH = 8
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)(
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input clk, // Input clock
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input rst,
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input sof, // Start of frame indicator marking the MS Beat
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input [WIDTH-1:0] idata, // Input data beat
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input ivalid, // Input data qualifier
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output reg [WIDTH*2-1:0] odata, // Output data beat
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output reg ovalid, // Output data qualifier
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output reg osof // Output Start of frame indicator
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);
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reg [WIDTH-1:0] idata_d = {WIDTH{1'b0}};
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always @(posedge clk) begin
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if (ivalid) begin
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idata_d <= idata;
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end
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end
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// Single clock mode:
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reg [6:0] sof_d = 7'b000;
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// Use sof_d[2] for frame size of 4 beats
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// Use sof_d[4,6] for frame size of 8 beats
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always @(posedge clk) begin
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if (rst) begin
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sof_d <= 7'b0;
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end else if (ivalid) begin
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sof_d <= {sof_d[5:0],sof};
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end
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if (ivalid &(sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6])) begin
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odata <= {idata_d,idata};
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end
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ovalid <= ivalid & (sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6]);
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osof <= ivalid & sof_d[0];
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end
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endmodule
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