221 lines
7.8 KiB
Verilog
221 lines
7.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module adrv9001_tx_link #(
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parameter CMOS_LVDS_N = 0,
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parameter CLK_DIV_IS_FAST_CLK = 0
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) (
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input dac_clk_div,
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output [7:0] dac_data_0,
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output [7:0] dac_data_1,
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output [7:0] dac_data_2,
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output [7:0] dac_data_3,
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output [7:0] dac_data_strobe,
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output [7:0] dac_data_clk,
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output dac_data_valid,
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// upper layer data interface
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output tx_clk,
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input tx_rst,
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input tx_data_valid,
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input [15:0] tx_data_i,
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input [15:0] tx_data_q,
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// Config interface
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input tx_sdr_ddr_n,
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input tx_single_lane,
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input tx_symb_op,
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input tx_symb_8_16b
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);
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assign tx_clk = dac_clk_div;
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wire [7:0] data32sdr;
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wire [7:0] strobe32sdr;
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wire [7:0] data16sdr_0;
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wire [7:0] strobe16sdr;
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wire [7:0] data8sdr_0;
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wire [7:0] data8sdr_1;
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wire [7:0] data8sdr_2;
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wire [7:0] data8sdr_3;
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wire [7:0] strobe8sdr;
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wire ld_next;
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reg [31:0] data32 = 32'b0;
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reg [31:0] strobe32 = 32'b0;
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reg [15:0] data16_0 = 16'b0;
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reg [15:0] data16_1 = 16'b0;
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reg [15:0] strobe16 = 16'b0;
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reg [7:0] data8_0 = 8'b0;
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reg [7:0] data8_1 = 8'b0;
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reg [7:0] data8_2 = 8'b0;
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reg [7:0] data8_3 = 8'b0;
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reg [7:0] strobe8 = 8'b0;
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reg [3:0] valid_gen = 4'b0;
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// Serialization factor Per data lane 32
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always @(posedge tx_clk) begin
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if (tx_data_valid) begin
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data32 <= {tx_data_i,tx_data_q};
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strobe32 <= {1'b1,31'b0};
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end else if (ld_next) begin
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if (tx_sdr_ddr_n) begin
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data32 <= {data32,4'b0};
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strobe32 <= {strobe32,4'b0};
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end else begin
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data32 <= {data32,8'b0};
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strobe32 <= {strobe32,8'b0};
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end
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end
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end
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// Double each bit due the DDR PHY
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assign data32sdr = {data32[31],data32[31],
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data32[30],data32[30],
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data32[29],data32[29],
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data32[28],data32[28]};
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assign strobe32sdr = {strobe32[31],strobe32[31],
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strobe32[30],strobe32[30],
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strobe32[29],strobe32[29],
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strobe32[28],strobe32[28]};
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// Serialization factor Per data lane 16
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always @(posedge tx_clk) begin
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if (tx_data_valid) begin
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data16_0 <= tx_data_i;
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data16_1 <= tx_data_q;
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strobe16 <= {1'b1,15'b0};
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end else if (ld_next) begin
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if(tx_sdr_ddr_n) begin
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data16_0 <= {data16_0,4'b0};
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data16_1 <= {data16_1,4'b0};
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strobe16 <= {strobe16,4'b0};
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end else begin
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data16_0 <= {data16_0,8'b0};
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data16_1 <= {data16_1,8'b0};
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strobe16 <= {strobe16,8'b0};
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end
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end
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end
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// Double each bit due to the DDR PHY
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assign data16sdr_0 = {data16_0[15],data16_0[15],
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data16_0[14],data16_0[14],
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data16_0[13],data16_0[13],
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data16_0[12],data16_0[12]};
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assign strobe16sdr = {strobe16[15],strobe16[15],
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strobe16[14],strobe16[14],
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strobe16[13],strobe16[13],
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strobe16[12],strobe16[12]};
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// Serialization factor Per data lane 8
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always @(posedge tx_clk) begin
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if (tx_data_valid) begin
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data8_0 <= tx_data_i[7:0];
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data8_1 <= tx_data_i[15:8];
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data8_2 <= tx_data_q[7:0];
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data8_3 <= tx_data_q[15:8];
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strobe8 <= {1'b1,7'b0};
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end else if (ld_next) begin
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data8_0 <= {data8_0,4'b0};
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data8_1 <= {data8_1,4'b0};
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data8_2 <= {data8_2,4'b0};
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data8_3 <= {data8_3,4'b0};
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strobe8 <= {strobe16,4'b0};
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end
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end
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// Double each bit due the DDR PHY
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assign data8sdr_0 = {data8_0[7],data8_0[7],
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data8_0[6],data8_0[6],
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data8_0[5],data8_0[5],
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data8_0[4],data8_0[4]};
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assign data8sdr_1 = {data8_1[7],data8_1[7],
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data8_1[6],data8_1[6],
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data8_1[5],data8_1[5],
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data8_1[4],data8_1[4]};
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assign data8sdr_2 = {data8_2[7],data8_2[7],
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data8_2[6],data8_2[6],
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data8_2[5],data8_2[5],
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data8_2[4],data8_2[4]};
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assign data8sdr_3 = {data8_3[7],data8_3[7],
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data8_3[6],data8_3[6],
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data8_3[5],data8_3[5],
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data8_3[4],data8_3[4]};
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assign strobe8sdr = {strobe8[7],strobe8[7],
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strobe8[6],strobe8[6],
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strobe8[5],strobe8[5],
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strobe8[4],strobe8[4]};
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assign dac_data_0 = tx_single_lane ? (tx_symb_op ? (tx_sdr_ddr_n ? data16sdr_0 : data16_0[15-:8]) :
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(tx_sdr_ddr_n ? data32sdr : data32[31-:8])) :
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(CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_0 : data8_0) : data16_0[15-:8]);
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assign dac_data_1 = tx_single_lane ? 'b0 :
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(CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_1 : data8_1) :
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data16_1[15-:8]);
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assign dac_data_2 = tx_single_lane ? 'b0 :
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(CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_2 : data8_2) :
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1'b0);
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assign dac_data_3 = tx_single_lane ? 'b0 :
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(CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_3 : data8_3) :
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1'b0);
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assign dac_data_strobe = tx_single_lane ? (tx_symb_op ? (tx_symb_8_16b ? (tx_sdr_ddr_n ? strobe8sdr : strobe8) :
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(tx_sdr_ddr_n ? strobe16sdr : strobe16[15-:8])):
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(tx_sdr_ddr_n ? strobe32sdr : strobe32[31-:8])) :
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(CMOS_LVDS_N ? (tx_sdr_ddr_n ? strobe8sdr : strobe8) : strobe16[15-:8]);
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assign dac_data_clk = {4{1'b1,1'b0}};
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assign dac_data_valid = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[3];
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always @(posedge tx_clk) begin
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if (tx_data_valid) begin
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valid_gen <= 4'b1000;
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end else begin
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valid_gen <= {valid_gen[2:0],valid_gen[3]};
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end
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end
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assign ld_next = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[2];
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endmodule
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