81 lines
3.1 KiB
ReStructuredText
81 lines
3.1 KiB
ReStructuredText
.. _spi_engine interconnect:
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SPI Engine Interconnect Module
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================================================================================
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.. hdl-component-diagram::
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The SPI Engine Interconnect module allows connecting multiple
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:ref:`spi_engine control-interface` masters to a single
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:ref:`spi_engine control-interface` slave.
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This enables multiple command stream generators to connect to a single
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:ref:`spi_engine execution` and consequential give them access to the same SPI bus.
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The interconnect modules take care of properly arbitrating between the different
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command streams.
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Combining multiple command stream generators in a design and connecting them to
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a single execution module allows for the creation of flexible and efficient
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designs using standard components.
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:widths: 25 75
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v`
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- Verilog source for the peripheral.
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* - :git-hdl:`library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl`
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- TCL script to generate the Vivado IP-integrator project for the
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peripheral.
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - DATA_WIDTH
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- Data width of the parallel SDI/SDO data interfaces.
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* - NUM_OF_SDI
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- Number of SDI lines on the physical SPI interface.
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Signal and Interface Pins
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - clk
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- A signals of the module are synchronous to this clock.
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* - resetn
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- Synchronous active-low reset.
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Resets the internal state of the module.
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* - s*_ctrl
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- :ref:`spi_engine control-interface` slave.
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| ``s0_ctrl`` connects to the first control interface master.
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| ``s1_ctrl`` connects to the second control interface master.
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* - m_ctrl
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- | :ref:`spi_engine control-interface` master.
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| Connects to the control interface slave.
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Theory of Operation
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--------------------------------------------------------------------------------
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The SPI Engine Interconnect module has multiple
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:ref:`spi_engine control-interface` slave ports and a single
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:ref:`spi_engine control-interface` master port.
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It can be used to connect multiple command stream generators to a single command
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execution engine. Arbitration between the streams is done on a priority
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basis, streams with a lower index have higher priority. This means if commands
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are present on two streams arbitration will be granted to the one with the lower
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index. Once arbitration has been granted the port it was granted to stays in
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control until it sends a SYNC command. When the interconnect module sees a SYNC
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command arbitration will be re-evaluated after the SYNC command has been
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completed. This makes sure that once a SPI transaction consisting of multiple
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commands has been started it is able to complete without being interrupted by a
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higher priority stream.
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