120 lines
3.5 KiB
ReStructuredText
120 lines
3.5 KiB
ReStructuredText
:orphan:
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.. _template_ip:
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IP Template
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================================================================================
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.. hdl-component-diagram::
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:path: library/spi_engine/spi_engine_execution
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Features
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--------------------------------------------------------------------------------
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* AXI-based configuration
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* Vivado and Quartus Compatible
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/axi_dmac/axi_dmac.v`
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- Verilog source for the peripheral.
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: ../axi_dmac/block_diagram.svg
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:alt: Template IP block diagram
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:align: center
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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:path: library/spi_engine/spi_engine_interconnect
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* - DATA_WIDTH
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- Data width of the parallel SDI/SDO data interfaces.
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.. _template_ip interface:
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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:path: library/axi_ad9783
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Detailed Architecture
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--------------------------------------------------------------------------------
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::
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.. image:: detailed_architecture.svg
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:alt: Template IP detailed architecture
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:align: center
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Detailed Description
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--------------------------------------------------------------------------------
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The top module instantiates
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* The ADC channel register map.
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* The ADC common register map.
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* The AXI handling interface.
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The data from the interface module is processed by the ADC channel module.
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The Up_adc_common module implements the ADC COMMON register map, allowing for
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basic monitoring and control of the ADC.
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The Up_adc_channel module implements the ADC CHANNEL register map, allowing for
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basic monitoring and control of the ADC's channel.
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Register Map
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--------------------------------------------------------------------------------
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.. hdl-regmap::
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:name: COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: ADC_COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: ADC_CHANNEL
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:no-type-info:
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Design Guidelines
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--------------------------------------------------------------------------------
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The control of the chip is done through an SPI interface, which is needed at the
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system level.
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The :ref:`template_ip interface` must be connected directly to the top file of
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the design, as IO primitives are part of the IP.
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The example design uses a DMA to move the data from the output of the IP to memory.
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If the data needs to be processed in HDL before moving to the memory, it can be
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done at the output of the IP (at the system level) or inside the ADC interface
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module (at the IP level).
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The example design uses a processor to program all the registers.
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If no processor is available in your system, you can create your IP starting
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from the interface module.
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Software Guidelines
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--------------------------------------------------------------------------------
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Linux is supported also using :git-linux:`master:/`.
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References
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--------------------------------------------------------------------------------
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* :git-hdl:`/`, :git-hdl:`library/axi_ad777x` library.
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* :git-linux:`master:/`.
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* :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`.
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* :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`.
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