234 lines
7.1 KiB
Verilog
Executable File
234 lines
7.1 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad3552r #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter DDS_DISABLE = 0,
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parameter DDS_TYPE = 1,
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parameter DDS_CORDIC_DW = 16,
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parameter DDS_CORDIC_PHASE_DW = 16
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) (
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// DAC INTERFACE
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input dac_clk,
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input [31:0] dma_data,
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input valid_in_dma,
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input valid_in_dma_sec,
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output dac_data_ready,
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input [15:0] data_in_a,
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input [15:0] data_in_b,
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input valid_in_a,
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input valid_in_b,
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output dac_sclk,
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output dac_csn,
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input [ 3:0] sdio_i,
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output [ 3:0] sdio_o,
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output sdio_t,
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// sync transfer between 2 DAC'S
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input external_sync,
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output sync_ext_device,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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// internal clocks and resets
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wire dac_rst_s;
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wire up_clk;
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wire up_rstn;
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// internal signals
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s;
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wire up_rack_s;
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wire [ 7:0] address;
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wire [23:0] data_read;
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wire [23:0] data_write;
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wire ddr_sdr_n;
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wire symb_8_16b;
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wire transfer_data;
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wire stream;
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wire [31:0] dac_data;
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wire dac_valid;
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wire if_busy;
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wire dac_ext_sync_arm;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// device interface
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axi_ad3552r_if axi_ad3552r_interface (
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.clk_in(dac_clk),
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.reset_in(dac_rst_s),
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.dac_data(dac_data),
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.dac_data_valid(dac_valid),
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.dac_data_valid_ext(valid_in_dma_sec),
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.dac_data_ready(dac_data_ready),
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.address(address),
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.data_read(data_read),
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.data_write(data_write),
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.sdr_ddr_n(sdr_ddr_n),
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.symb_8_16b(symb_8_16b),
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.transfer_data(transfer_data),
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.stream(stream),
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.if_busy(if_busy),
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.external_sync(external_sync),
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.external_sync_arm(dac_ext_sync_arm),
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.sync_ext_device(sync_ext_device),
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.sclk(dac_sclk),
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.csn(dac_csn),
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.sdio_i(sdio_i),
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.sdio_o(sdio_o),
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.sdio_t(sdio_t));
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// core
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axi_ad3552r_core #(
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.ID(ID),
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.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
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.FPGA_FAMILY(FPGA_FAMILY),
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.SPEED_GRADE(SPEED_GRADE),
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.DEV_PACKAGE(DEV_PACKAGE),
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.DDS_DISABLE(DDS_DISABLE),
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.DDS_TYPE(DDS_TYPE),
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.DDS_CORDIC_DW(DDS_CORDIC_DW),
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.DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW)
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) axi_ad3552r_up_core (
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.dac_clk(dac_clk),
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.dac_rst(dac_rst_s),
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.adc_data_in_a(data_in_a),
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.adc_data_in_b(data_in_b),
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.dma_data(dma_data),
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.adc_valid_in_a(valid_in_a),
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.adc_valid_in_b(valid_in_b),
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.valid_in_dma(valid_in_dma),
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.dac_data_ready(dac_data_ready),
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.dac_data(dac_data),
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.dac_valid(dac_valid),
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.address(address),
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.data_read(data_read),
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.data_write(data_write),
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.sdr_ddr_n(sdr_ddr_n),
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.symb_8_16b(symb_8_16b),
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.transfer_data(transfer_data),
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.stream(stream),
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.dac_ext_sync_arm(dac_ext_sync_arm),
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.if_busy(if_busy),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq(up_wreq_s),
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.up_waddr(up_waddr_s),
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.up_wdata(up_wdata_s),
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.up_wack(up_wack_s),
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.up_rreq(up_rreq_s),
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.up_raddr(up_raddr_s),
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.up_rdata(up_rdata_s),
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.up_rack(up_rack_s));
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// up bus interface
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up_axi i_up_axi(
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq_s),
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.up_waddr(up_waddr_s),
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.up_wdata(up_wdata_s),
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.up_wack(up_wack_s),
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.up_rreq(up_rreq_s),
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.up_raddr(up_raddr_s),
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.up_rdata(up_rdata_s),
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.up_rack(up_rack_s));
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endmodule
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